SOIC
M
AC86M
CD74AC86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
SCHS324 – JANUARY 2003
D
AC Types Feature 1.5-V to 5.5-V Operation
and Balanced Noise Immunity at 30% of the
E OR M PACKAGE
(TOP VIEW)
Supply
D
Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
D
Balanced Propagation Delays
D
±24-mA Output Drive Current
– Fanout to 15 F Devices
D
SCR-Latchup-Resistant CMOS Process and
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
V
CC
4B
4A
4Y
3B
3A
9
3Y
8
Circuit Design
D
Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
description/ordering information
The CD74AC86 is a quadruple 2-input exclusive-OR gate. This device performs the Boolean function
Y = A ⊕ B or Y = A
A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced
in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the
output.
–55°C to 125°C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
B + AB in positive logic.
T
A
PDIP – E Tube CD74AC86E CD74AC86E
PACKAGE
–
ORDERING INFORMATION
†
Tube CD74AC86M
Tape and reel CD74AC86M96
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
FUNCTION TABLE
(each gate)
INPUTS
A B
L L L
L HH
H LH
H H L
OUTPUT
Y
Copyright 2003, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
CD74AC86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
SCHS324 – JANUARY 2003
exclusive-OR logic
An exclusive-OR gate has many applications, some of which can be represented better by alternative
logic symbols.
EXCLUSIVE OR
= 1
These are five equivalent exclusive-OR symbols valid for an CD74AC86 gate in positive logic; negation may be shown at any two ports.
LOGIC-IDENTITY ELEMENT EVEN-PARITY ELEMENT ODD-PARITY ELEMENT
= 2k 2k + 1
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
The output is active (high) if
an odd number of inputs
(i.e., only 1 of the 2) are
active.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
–0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
IK
(V
OK
< 0 or V
I
(V
O
O
> VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
< 0 or V
(V
O
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
JA
> VCC) (see Note 1) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
= 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): E package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
∆t/∆v
Input transition rise or fall rate
ns/V
CC
CD74AC86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
SCHS324 – JANUARY 2003
recommended operating conditions (see Note 3)
TA = 25°C
MIN MAX MIN MAX MIN MAX
V
V
V
V
V
I
OH
I
OL
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 1.5 5.5 1.5 5.5 1.5 5.5 V
CC
VCC = 1.5 V 1.2 1.2 1.2
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
High-level output current VCC = 4.5 V to 5.5 V –24 –24 –24 mA
Low-level output current VCC = 4.5 V to 5.5 V 24 24 24 mA
p
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
VCC = 3 V
VCC = 5.5 V 3.85 3.85 3.85
VCC = 1.5 V 0.3 0.3 0.3
VCC = 3 V
VCC = 5.5 V 1.65 1.65 1.65
VCC = 1.5 V to 3 V 50 50 50
VCC = 3.6 V to 5.5 V 20 20 20
2.1 2.1 2.1
–55°C to
125°C
0.9 0.9 0.9
CC
CC
0 V
0 V
CC
CC
–40°C to
85°C
0 V
0 V
CC
CC
UNIT
V
V
V
V
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS V
1.5 V 1.4 1.4 1.4
IOH = –50 µA
V
OH
V
OL
I
I
I
CC
C
†
i
T est one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize
power dissipation. T est verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.
VI = VIH or V
VI = VIH or V
VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
VI = VCC or GND, IO = 0 5.5 V 4 80 40 µA
IL
IL
IOH = –4 mA 3 V 2.58 2.4 2.48
IOH = –24 mA 4.5 V 3.94 3.7 3.8
IOH = –50 mA
IOH = –75 mA
IOL = 50 µA
IOL = 12 mA 3 V 0.36 0.5 0.44
IOL = 24 mA 4.5 V 0.36 0.5 0.44
IOL = 50 mA
IOL = 75 mA
†
†
†
†
3 V 2.9 2.9 2.9
4.5 V 4.4 4.4 4.4
5.5 V 3.85
5.5 V 3.85
1.5 V 0.1 0.1 0.1
3 V 0.1 0.1 0.1
4.5 V 0.1 0.1 0.1
5.5 V 1.65
5.5 V 1.65
TA = 25°C
MIN MAX MIN MAX MIN MAX
–55°C to
125°C
10 10 10 pF
–40°C to
85°C
UNIT
V
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
CD74AC86
(INPUT)
(OUTPUT)
A or B
Y
ns
(INPUT)
(OUTPUT)
A or B
Y
ns
(INPUT)
(OUTPUT)
A or B
Y
ns
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
SCHS324 – JANUARY 2003
switching characteristics over recommended operating free-air temperature range,
V
= 1.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
CC
–55°C to
125°C
MIN MAX MIN MAX
PARAMETER
t
PLH
t
PHL
FROM
TO
switching characteristics over recommended operating free-air temperature range,
VCC = 3 V ± 0.3 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
–55°C to
125°C
MIN MAX MIN MAX
3.8 15.1 3.9 13.7
3.8 15.1 3.9 13.7
PARAMETER
t
PLH
t
PHL
FROM
TO
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
–55°C to
125°C
MIN MAX MIN MAX
2.7 10.8 2.8 9.8
2.7 10.8 2.8 9.8
PARAMETER
t
PLH
t
PHL
FROM
TO
–40°C TO
135 123
135 123
–40°C TO
–40°C TO
85°C
85°C
85°C
UNIT
UNIT
UNIT
operating characteristics, TA = 25°C
C
Power dissipation capacitance 57 pF
pd
PARAMETER TYP UNIT
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CD74AC86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE
SCHS324 – JANUARY 2003
PARAMETER MEASUREMENT INFORMATION
S1
50% V
t
r
CC
t
f
†
†
CC
t
rec
50% V
50% V
t
PHL
t
PLH
.
dis
CC
CC
50%
From Output
Under Test
CL = 50 pF
(see Note A)
†
When VCC = 1.5 V, R1 = R2 = 1 kΩ
CLR
Input
CLK
VOLTAGE WAVEFORMS
Input
In-Phase
Output
Out-of-Phase
Output
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. For clock inputs, f
E. The outputs are measured one at a time with one input transition per measurement.
F. t
G. t
H. t
I. All parameters and waveforms are not applicable to all devices.
50% V
t
PLH
t
PHL
VOLTAGE WAVEFORMS
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
Phase relationships between waveforms are arbitrary.
and t
PLH
PZL
PLZ
and t
and t
PHL
PZH
PHZ
R1 = 500 Ω
R2 = 500 Ω
LOAD CIRCUIT
RECOVERY TIME
CC
50%
90% 90%
50% V
10% 10%
is measured with the input duty cycle at 50%.
max
are the same as tpd.
are the same as ten.
are the same as t
2 × V
Open
GND
50% V
10%10%
90%90%
V
0 V
V
0 V
CC
CC
CC
t
t
TEST S1
t
w
50% V
50% V
50% V
Open
2 × V
GND
CC
50% V
CC
t
h
CC
CC
CC
50% V
50% V
20% V
80% V
CC
50% V
10%10%
t
CC
t
PLZ
t
PHZ
V
0 V
f
CC
CC
CC
V
0 V
V
CC
0 V
V
0 V
≈V
V
V
≈0 V
CC
CC
CC
CC
OL
OH
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Input
Reference
Input
Data
Input
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
V
CC
0 V
V
OH
CC
V
OL
f
V
OH
V
OL
r
Waveform 1
S1 at 2 × V
(see Note B)
Waveform 2
(see Note B)
50%
Output
Control
Output
Output
S1 at GND
OUTPUT ENABLE AND DISABLE TIMES
50% V
CC
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
90% 90%
t
r
VOLTAGE WAVEFORMS
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2007
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
CD74AC86E ACTIVE PDIP N 14 25 Pb-Free
CD74AC86EE4 ACTIVE PDIP N 14 25 Pb-Free
CD74AC86M ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br)
CD74AC86M96 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br)
CD74AC86M96E4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br)
CD74AC86M96G4 ACTIVE SOIC D 14 2500 Green (RoHS &
no Sb/Br)
CD74AC86ME4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br)
CD74AC86MG4 ACTIVE SOIC D 14 50 Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(RoHS)
(RoHS)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
(3)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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