TEXAS INSTRUMENTS CD74AC280, CD74ACT280 Technical data

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Data sheet acquired from Harris Semiconductor
SCHS250A

CD54/74AC280,

CD54/74ACT280

August 1998 - Revised May 2000

Features

• Buffered Inputs

• Typical Propagation Delay

- 10ns at V

= 5V, TA = 25oC, CL = 50pF

CC

• Exceeds 2kV ESD Protection per MIL-STD-883,
Method 3015

• SCR-Latchup-Resistant CMOS Process and Circuit
Design

• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption

• Balanced Propagation Delays

• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply

• ±24mA Output Drive Current

- Fanout to 15 FAST™ ICs

- Drives 50Ω Transmission Lines

Description

The ’AC280 and ’ACT280 are 9-bit odd/even parity genera­tor/checkers that utilize Advanced CMOS Logic technology.
Both even and odd parity outputs are available for checking
or generating parity for words up to nine bits long. Even par­ity is indicated (∑E output is HIGH) when an even number of

9-Bit Odd/Even Parity Generator/Checker

data inputs is HIGH. Odd parity is indicated (∑O output is
HIGH) when an odd number of data inputs is HIGH. Parity
checking for words larger than nine bits can be accom­plished by tying the ∑E output to any input of an additional
’AC280, ’ACT280 parity checker.

Ordering Information

PART

NUMBER

CD54AC280F3A -55 to 125 14 Ld CERDIP
CD74AC280E 0 to 70oC, -40 to 85,

CD74AC280M 0 to 70oC, -40 to 85,

CD54ACT280F3A -55 to 125 14 Ld CERDIP
CD74ACT280E 0 to 70oC, -40 to 85,

CD74ACT280M 0 to 70oC, -40 to 85,

NOTES:

1. When ordering,use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer and die for thispart number is availablewhich meets all elec­trical specifications. Pleasecontact your localTI salesoffice or cus­tomer service for ordering information.

TEMP.

RANGE (oC) PACKAGE

14 Ld PDIP

-55 to 125
14 Ld SOIC

-55 to 125

14 Ld PDIP

-55 to 125
14 Ld SOIC

-55 to 125

Pinout

CD54AC280, CD54ACT280

(CERDIP)

CD74AC280, CD74ACT280

(PDIP, SOIC)

TOP VIEW

I6

1
2

I7

3

NC

4

I8

5

∑E

6

∑O

7

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.

Copyright

© 2000, Texas Instruments Incorporated

14

V

CC

I5

13
12

I4

11

I3

10

I2

9

I1

8

I0

Functional Diagram

8

I0

9

I1

10

I2

11

I3

12

I4

13

I5

1

I6

2

I7

4

I8

1

5

∑ EVEN

6

∑ ODD

GND = 7
V

= 14

CC

NC = 3

CD54/74AC280, CD54/74ACT280

F

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC VCC or Ground Current, I

CC orIGND

(Note 3) . . . . . . . . .±100mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC (Note 4)

AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V

ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Slew Rate, dt/dv

AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)

AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)

ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

3. For up to 4 outputs per device, add ±25mA for each additional output.

4. Unless otherwise specified, all voltages are referenced to ground.

5. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 5) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ___

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ___

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

CC

DC Electrical Specifications

PARAMETER SYMBOL

AC TYPES

High Level Input Voltage V

Low Level Input Voltage V

High Level Output Voltage V

IH

IL

OH

TEST

CONDITIONS

(V) IO(mA) MIN MAX MIN MAX MIN MAX

I

V

CC

(V)

25

o

C

-40oC TO
85oC

-55oC TO
125oC

- - 1.5 1.2 - 1.2 - 1.2 - V
3 2.1 - 2.1 - 2.1 - V

5.5 3.85 - 3.85 - 3.85 - V

- - 1.5 - 0.3 - 0.3 - 0.3 V
3 - 0.9 - 0.9 - 0.9 V

5.5 - 1.65 - 1.65 - 1.65 V

VIH or V

-0.05 1.5 1.4 - 1.4 - 1.4 - V

IL

-0.05 3 2.9 - 2.9 - 2.9 - V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

-4 3 2.58 - 2.48 - 2.4 - V

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

5.5 - - 3.85 - - - V

(Note 6, 7)

-50

5.5----3.85 - V

(Note 6, 7)

UNITSV

2

CD54/74AC280, CD54/74ACT280

DC Electrical Specifications (Continued)

PARAMETER SYMBOL

Low Level Output Voltage V

OL

TEST

CONDITIONS

(V) IO(mA) MIN MAX MIN MAX MIN MAX

I

VIH or V

0.05 1.5 - 0.1 - 0.1 - 0.1 V

IL

V

CC

(V)

25

o

C

0.05 3 - 0.1 - 0.1 - 0.1 V

0.05 4.5 - 0.1 - 0.1 - 0.1 V
12 3 - 0.36 - 0.44 - 0.5 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75

5.5 - - - 1.65 - - V

(Note 6, 7)

50

5.5-----1.65 V

(Note 6, 7)

Input Leakage Current I

I

VCC or

- 5.5 - ±0.1 - ±1-±1 µA

GND

Quiescent Supply Current
MSI

I

CC

VCC or

GND

0 5.5 - 8 - 80 - 160 µA

ACT TYPES

High Level Input Voltage V

IH

- - 4.5 to

2-2-2-V

5.5

Low Level Input Voltage V

IL

- - 4.5 to

- 0.8 - 0.8 - 0.8 V

5.5

High Level Output Voltage V

OH

VIH or V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

IL

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

5.5 - - 3.85 - - - V

(Note 6, 7)

-50

5.5----3.85 - V

(Note 6, 7)

Low Level Output Voltage V

OL

VIH or V

0.05 4.5 - 0.1 - 0.1 - 0.1 V

IL

24 4.5 - 0.36 - 0.44 - 0.5 V
75

5.5 - - - 1.65 - - V

(Note 6, 7)

50

5.5-----1.65 V

(Note 6, 7)

Input Leakage Current I

I

VCC or

- 5.5 - ±0.1 - ±1-±1 µA

GND

Quiescent Supply Current
MSI

AdditionalSupply Current per
Input Pin TTL Inputs High

I

CC

VCC or

GND

∆I

CC

V

CC

-2.1

0 5.5 - 8 - 80 - 160 µA

- 4.5 to

- 2.4 - 2.8 - 3 mA

5.5

1 Unit Load

NOTES:

6. Testone output at a time for a1-second maximum duration. Measurement is made byforcing current and measuring voltage to minimize
power dissipation.

7. Test verifies a minimum 50Ω transmission-line-drive capability at 85

o

C, 75Ω at 125oC.

-40oC TO
85oC

-55oC TO
125oC

UNITSV

ACT Input Load Table

INPUT UNIT LOAD

All 1.43

NOTE: Unitload is ∆ICClimit specified inDC ElectricalSpecifications
Table, e.g., 2.4mA max at 25oC.

3

CD54/74AC280, CD54/74ACT280

Switching Specifications Input t

, tf = 3ns, CL= 50pF (Worst Case)

r

-40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL VCC (V)

AC TYPES

Propagation Delay,
Any Input to ∑O

t

PLH

, t

PHL

1.5 - - 239 - - 263 ns

3.3

7.5 - 26 7.3 - 29 ns

(Note 9)

5

5.4 - 19.1 5.3 - 21 ns

(Note 10)

Propagation Delay,
Any Input to ∑E

t

PLH

, t

PHL

1.5 - - 227 - - 250 ns

3.3 7.2 - 25 7 - 28 ns
5 5.2 - 18.2 5 - 20 ns

Input Capacitance C
Power Dissipation Capacitance C

I

PD

- - -10- -10pF

- - 115 - - 115 - pF

(Note 11)

ACT TYPES

Propagation Delay,
Any Input to ∑O

Propagation Delay,

t

PLH

t

PLH

, t

PHL

5

5.6 - 19.6 5.4 - 21.6 ns

(Note 10)

, t

PHL

5 5.6 - 19.6 5.4 - 21.6 ns

Any Input to ∑E
Input Capacitance C
Power Dissipation Capacitance C

I

PD

- - -10- -10pF

- - 115 - - 115 - pF

(Note 11)

NOTES:

8. Limits tested 100%

9. 3.3V Min is at 3.6V, Max is at 3V.

10. 5V Min is at 5.5V, Max is at 4.5V.

11. CPD is used to determine the dynamic power consumption per package.
AC: PD = V
ACT: PD = V

2

fi(CPD + CL)

CC

2

fi(CPD + CL) + VCC∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

CC

UNITSMIN TYP MAX MIN TYP MAX

INPUT

LEVEL

I

n

0V

ΣO

0V

ΣE

0V

10%

OUTPUT

DUT

OUTPUT

LOAD

R

L

C

L

50pF

(NOTE)
500Ω

V

S

V

tr = 3ns

t

PHL

S

tf = 3ns

V

S

10%

t

PLH

V

S

NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.

AC ACT

t

PLH

V

S

FIGURE 1.

t

PHL

V

S

Input Level V
Input Switching Voltage, V
Output Switching Voltage, V

S

S

0.5 V

0.5 V

CC

CC
CC

3V

1.5V

0.5 V

CC

FIGURE 2. PROPAGATION DELAY TIMES

4

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Copyright © 2007, Texas Instruments Incorporated

PACKAGE OPTION ADDENDUM

www.ti.com

9-Oct-2007

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

CD54AC280F3A ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type

CD54ACT280F3A ACTIVE CDIP J 14 1 TBD A42 SNPB N/ A for Pkg Type

CD74AC280E ACTIVE PDIP N 14 25 Pb-Free

CD74AC280EE4 ACTIVE PDIP N 14 25 Pb-Free

CD74AC280M ACTIVE SOIC D 14 50 Green (RoHS &

no Sb/Br)

CD74AC280M96 ACTIVE SOIC D 14 2500 Green (RoHS &

no Sb/Br)

CD74AC280M96E4 ACTIVE SOIC D 14 2500 Green (RoHS &

no Sb/Br)

CD74AC280M96G4 ACTIVE SOIC D 14 2500 Green (RoHS &

no Sb/Br)

CD74AC280ME4 ACTIVE SOIC D 14 50 Green (RoHS &

no Sb/Br)

CD74AC280MG4 ACTIVE SOIC D 14 50 Green (RoHS &

no Sb/Br)

CD74ACT280E ACTIVE PDIP N 14 25 Pb-Free

CD74ACT280EE4 ACTIVE PDIP N 14 25 Pb-Free

CD74ACT280M ACTIVE SOIC D 14 50 Green (RoHS &

no Sb/Br)

CD74ACT280M96 ACTIVE SOIC D 14 2500 Green (RoHS &

no Sb/Br)

CD74ACT280M96E4 ACTIVE SOIC D 14 2500 Green (RoHS &

no Sb/Br)

CD74ACT280M96G4 ACTIVE SOIC D 14 2500 Green (RoHS &

no Sb/Br)

CD74ACT280ME4 ACTIVE SOIC D 14 50 Green (RoHS &

no Sb/Br)

CD74ACT280MG4 ACTIVE SOIC D 14 50 Green (RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU N / A for Pkg Type

CU NIPDAU N / A for Pkg Type

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU N / A for Pkg Type

CU NIPDAU N / A for Pkg Type

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

(3)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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to Customer on an annual basis.

9-Oct-2007

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

TAPE AND REEL BOX INFORMATION

4-Oct-2007

Device Package Pins Site Reel

Diameter

(mm)

CD74AC280M96 D 14 SITE 41 330 16 6.5 9.0 2.1 8 16 Q1

CD74ACT280M96 D 14 SITE 41 330 16 6.5 9.0 2.1 8 16 Q1

Reel

Width

(mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

4-Oct-2007

Device Package Pins Site Length (mm) Width (mm) Height (mm)

CD74AC280M96 D 14 SITE 41 346.0 346.0 33.0

CD74ACT280M96 D 14 SITE 41 346.0 346.0 33.0

Pack Materials-Page 2