Texas Instruments CD74ACT273SM96, CD74ACT273SM, CD74ACT273M96, CD74ACT273M, CD74ACT273E Datasheet

CD54AC273, CD74AC273

Data sheet acquired from Harris Semiconductor
SCHS249A

CD54ACT273, CD74ACT273

August 1998 - Revised April 2000

Features

• Buffered Inputs

• Typical Propagation Delay

- 6.5ns at V

= 5V, TA = 25oC, CL = 50pF

CC

• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015

• SCR-Latchup-Resistant CMOS Process and Circuit
Design

• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption

• Balanced Propagation Delays

• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply

• ±24mA Output Drive Current

- Fanout to 15 FAST™ ICs

- Drives 50Ω Transmission Lines

Pinout

CD54AC273, CD54ACT273

(CDIP)

CD74AC273, CD74ACT273

(PDIP, SOIC)

TOP VIEW

Octal D Flip-Flop with Reset

Description

The ’AC273 and ’ACT273 devices are octal D-type flip-flops
with reset that utilize advanced CMOS logic technology.
Information at the D input is transferred to the Q output on
the positive-going edge of the clock pulse. All eight flip-flops
are controlled by a common clock (CP) and a common reset
(

MR). Resetting is accomplished by a low voltage level

independent of the clock.

Ordering Information

PART

NUMBER

CD74AC273E -40oC to 85oC 20 Ld PDIP
CD54AC273F3A -55oC to 125oC 20 Ld CDIP
CD74ACT273E -40oC to 85oC 20 Ld PDIP
CD54ACT273F3A -55oC to 125oC 20 Ld CDIP
CD74AC273M -40oC to 85oC 20 Ld SOIC
CD74ACT273M -40oC to 85oC 20 Ld SOIC

NOTES:

1. When ordering, use the entirepartnumber. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Waferand die for this part number is available which meets all
electrical specifications. Please contact your local sales office for
ordering information.

TEMPERATURE

RANGE PACKAGE

1

MR

Q0

2

D0

3

D1

4

Q1

5

Q2

6

D2

7
8

D3

9

Q3

GND

10

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.

Copyright

© 2000, Texas Instruments Incorporated

V

20

CC

Q7

19

D7

18

D6

17

Q6

16

Q5

15

D5

14

D4

13
12

Q4

11

CP

1

CD54AC273, CD74AC273, CD54ACT273, CD74ACT273

Functional Diagram

CLOCK

CP

DAT A

INPUTS

RESET MR

D0
D1
D2
D3
D4
D5
D6
D7

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

DAT A
OUTPUTS

TRUTH TABLE

INPUTS OUTPUTS

RESET

(MR)

CLOCK

CP

DATA

Dn Qn

LXXL
H ↑ HH
H ↑ LL
HLXQ0

H = High level (steady state), L = Low level (steady state), X = Irrel­evant, ↑ = Transition from Low to High level, Q0 = The level of Q
before the indicated steady-state input conditions were estab­lished.

2

CD54AC273, CD74AC273, CD54ACT273, CD74ACT273

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC VCC or Ground Current, I

CC orIGND

(Note 3) . . . . . . . . .±100mA

Operating Conditions

Temperature Range, T

CD54AC273, CD54ACT273 . . . . . . . . . . . . . . . . .-55oC to 125oC

CD74AC273, CD74ACT273 . . . . . . . . . . . . . . . . . .-40oC to 85oC

Supply Voltage Range, VCC (Note 4)

AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V

ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Slew Rate, dt/dv

AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)

AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)

ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

3. For up to 4 outputs per device, add ±25mA for each additional output.

4. Unless otherwise specified, all voltages are referenced to ground.

5. The package thermal impedance is calculated in accordance with JESD 51.

A

Thermal Resistance, θJA(Typical, Note 5)

E Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69oC/W

M Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58oC/W

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

CC

DC Electrical Specifications

PARAMETER SYMBOL

AC TYPES

High Level Input Voltage V

Low Level Input Voltage V

High Level Output Voltage V

IH

IL

OH

TEST

CONDITIONS

(V) IO(mA) MIN MAX MIN MAX MIN MAX

I

V

CC

(V)

25

o

C

-40oC TO
85oC

-55oC TO
125oC

- - 1.5 1.2 - 1.2 - 1.2 - V
3 2.1 - 2.1 - 2.1 - V

5.5 3.85 - 3.85 - 3.85 - V

- - 1.5 - 0.3 - 0.3 - 0.3 V
3 - 0.9 - 0.9 - 0.9 V

5.5 - 1.65 - 1.65 - 1.65 V

VIH or V

-0.05 1.5 1.4 - 1.4 - 1.4 - V

IL

-0.05 3 2.9 - 2.9 - 2.9 - V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

-4 3 2.58 - 2.48 - 2.4 - V

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

5.5 - - 3.85 - - - V

(Note 6, 7)

-50

5.5----3.85 - V

(Note 6, 7)

UNITSV

3

CD54AC273, CD74AC273, CD54ACT273, CD74ACT273

DC Electrical Specifications (Continued)

PARAMETER SYMBOL

Low Level Output Voltage V

OL

TEST

CONDITIONS

(V) IO(mA) MIN MAX MIN MAX MIN MAX

I

VIH or V

0.05 1.5 - 0.1 - 0.1 - 0.1 V

IL

V

CC

(V)

25

o

C

0.05 3 - 0.1 - 0.1 - 0.1 V

0.05 4.5 - 0.1 - 0.1 - 0.1 V
12 3 - 0.36 - 0.44 - 0.5 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75

5.5 - - - 1.65 - - V

(Note 6, 7)

50

5.5-----1.65 V

(Note 6, 7)

Input Leakage Current I

I

VCC or

- 5.5 - ±0.1 - ±1-±1 µA

GND

Quiescent Supply Current
MSI

I

CC

VCC or

GND

0 5.5 - 8 - 80 - 160 µA

ACT TYPES

High Level Input Voltage V

IH

- - 4.5 to

2-2-2-V

5.5

Low Level Input Voltage V

IL

- - 4.5 to

- 0.8 - 0.8 - 0.8 V

5.5

High Level Output Voltage V

OH

VIH or V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

IL

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

5.5 - - 3.85 - - - V

(Note 6, 7)

-50

5.5----3.85 - V

(Note 6, 7)

Low Level Output Voltage V

OL

VIH or V

0.05 4.5 - 0.1 - 0.1 - 0.1 V

IL

24 4.5 - 0.36 - 0.44 - 0.5 V
75

5.5 - - - 1.65 - - V

(Note 6, 7)

50

5.5-----1.65 V

(Note 6, 7)

Input Leakage Current I

I

VCC or

- 5.5 - ±0.1 - ±1-±1 µA

GND

Quiescent Supply Current
MSI

AdditionalSupply Current per
Input Pin TTL Inputs High

I

CC

VCC or

GND

∆I

CC

V

CC

-2.1

0 5.5 - 8 - 80 - 160 µA

- 4.5 to

- 2.4 - 2.8 - 3 mA

5.5

1 Unit Load

NOTES:

6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.

7. Test verifies a minimum 50Ω transmission-line-drive capability at 85

o

C, 75Ω at 125oC.

-40oC TO
85oC

-55oC TO
125oC

UNITSV

ACT Input Load Table

INPUT UNIT LOAD

Dn 0.5

MR 0.57

CP 1

NOTE: Unit load is ∆ICClimit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.

4

CD54AC273, CD74AC273, CD54ACT273, CD74ACT273

Prerequisite For Switching Function

PARAMETER SYMBOL VCC (V)

AC TYPES

Data to CP Set-Up Time t

Hold Time t

Removal Time, MR to CP t

MR Pulse Width t

CP Pulse Width t

CP Frequency f

ACT TYPES

Data to CP Set-Up Time t

Hold Time t
Removal Time MR to CP t
MR Pulse Width t
CP Pulse Width t
CP Frequency f

SU

H

REM

W

W

MAX

SU

H

REM

W
W

MAX

-40oC TO 85oC -55oC TO 125oC
UNITSMIN MAX MIN MAX

1.5 2 - 2 - ns

3.3

2-2-ns

(Note 9)

5

2-2-ns

(Note 10)

1.5 2 - 2 - ns

3.3 2 - 2 - ns
52-2-ns

1.5 2 - 2 - ns

3.3 2 - 2 - ns
52-2-ns

1.5 55 - 63 - ns

3.3 6.1 - 7 - ns
5 4.4 - 5 - ns

1.5 55 - 63 - ns

3.3 6.1 - 7 - ns
5 4.4 - 5 - ns

1.5 9 - 8 - MHz

3.3 81 - 71 - MHz
5 114 - 100 - MHz

5

2-2-ns

(Note 10)

52-2-ns
52-2-ns
5 4.4 - 5 - ns
5 5.3 - 6 - ns
5 97 - 85 - MHz

Switching Specifications Input t

PARAMETER SYMBOL VCC (V)

AC TYPES

Propagation Delay,
CP to Qn

t

PLH

, tf = 3ns, CL= 50pF (Worst Case)

r

, t

PHL

1.5 - - 154 - - 169 ns

3.3

4.9 - 17.2 4.7 - 18.9 ns

(Note 9)

5

3.5 - 12.3 3.4 - 13.5 ns

(Note 10)

5

-40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX

CD54AC273, CD74AC273, CD54ACT273, CD74ACT273

Switching Specifications Input t

, tf = 3ns, CL= 50pF (Worst Case) (Continued)

r

-40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL VCC (V)

Propagation Delay,
MR to Qn

t

PLH

, t

PHL

1.5 - - 154 - - 169 ns

3.3 4.9 - 17.2 4.7 - 18.9 ns
5 3.5 - 12.3 3.4 - 13.5 ns

Input Capacitance C
Power Dissipation Capacitance C

I

PD

- - -10- -10pF

- - 45 - - 45 - pF

(Note 11)

ACT TYPES

Propagation Delay,
CP to Qn

Propagation Delay,

t

PLH

t

PLH

, t

PHL

5

3.5 - 12.3 3.4 - 13.5 ns

(Note 10)

, t

PHL

5 3.5 - 12.3 3.4 - 13.5 ns

MR to Qn
Input Capacitance C
Power Dissipation Capacitance C

I

PD

- - -10- -10pF

- - 45 - - 45 - pF

(Note 11)

NOTES:

8. Limits tested 100%.

9. 3.3V Min is at 3.6V, Max is at 3V.

10. 5V Min is at 5.5V, Max is at 4.5V.

11. CPD is used to determine the dynamic power consumption per flip-flop.
AC: PD = CPD V
ACT: PD=CPDV

2

fi= ∑ (CL V

CC

2

CC

fi+ ∑ (CLV

2

fo)

CC

2

fo)+VCC∆ICCwhere fi= input frequency, fo= output frequency, CL= output load capacitance,

CC

VCC = supply voltage.

UNITSMIN TYP MAX MIN TYP MAX

INPUT

LEVEL

CP

Q

10%

90%
V

S

t

t

r

PHL

t

f

V

S

10%

t

W

V

S

V

S

t

PLH

V

S

FIGURE 1. PROPAGATION DELAY TIMES AND CLOCK

PULSE WIDTH

INPUT

LEVEL

MR

GND

INPUT

CP

(

Q)

Q

V

t

S

PLH

V

S

t

t

W

V

S

REM

V

S

FIGURE 2. PREREQUISITE AND PROPAGATION DELAY

TIMES FOR MASTER RESET

6

CD54AC273, CD74AC273, CD54ACT273, CD74ACT273

OUTPUT

LEVEL

D

V

S

tSU(L)

CP

FIGURE 3. PREREQUISITE FOR CLOCK

DUT

V

S

V

S

OUTPUT

V

S

(L)

t

H

R

L

tSU(H)

(NOTE)
500Ω

V

S

tH(H)

V

S

OUTPUT

LOAD

C

L

50pF

NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.

AC ACT

Input Level V
Input Switching Voltage, V
Output Switching Voltage, V

S

S

0.5 V

0.5 V

CC

CC
CC

FIGURE 4. PROPAGATION DELAY TIMES

3V

1.5V

0.5 V

CC

7

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Copyright  2000, Texas Instruments Incorporated