Texas Instruments CD74AC251M96, CD74AC251M Datasheet

1

Data sheet acquired from Harris Semiconductor
SCHS246

Features

• Buffered Inputs

• Typical Propagation Delay

- 6ns at V

CC

= 5V, TA = 25oC, CL = 50pF

• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015

• SCR-Latchup-Resistant CMOS Process and Circuit
Design

• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption

• Balanced Propagation Delays

• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply

• ±24mA Output Drive Current

- Fanout to 15 FAST™ ICs

- Drives 50Ω Transmission Lines

Pinout

CD74AC251, CD74ACT251

(PDIP, SOIC)

TOP VIEW

Description

The CD74AC251 and CD74ACT251 8-input multiplexers that
utilize the Harris Advanced CMOS Logic technology. This
multiplexerfeatures both true (Y) and complement (

Y) outputs

as well as an Output Enable (

OE) input. The OE must be at a

LOW logic level to enable this device. When the

OE input is
HIGH, both outputs are in the high-impedance state. When
enabled, address information on the data select inputs deter­mines which data input is routed to the Y and

Y outputs.

14

15

16

9

13
12
11
10

1
2
3
4
5

7

6

8

I

3

I

2

I

1

I

0

Y
Y

GND

OE

V

CC

I

5

I

6

I

7

S0
S1
S2

I

4

Ordering Information

PART

NUMBER

TEMP.

RANGE (oC) PACKAGE

PKG.

NO.

CD74AC251E 0 to 70oC, -40 to 85,

-55 to 125

16 Ld PDIP E16.3

CD74ACT251E 0 to 70oC, -40 to 85,

-55 to 125

16 Ld PDIP E16.3

CD74AC251M 0 to 70oC, -40 to 85,

-55 to 125

16 Ld SOIC M16.15

CD74ACT251M 0 to 70oC, -40 to 85,

-55 to 125

16 Ld SOIC M16.15

NOTES:

1. When ordering, usethe entire part number.Add the suffix 96to
obtain the variant in the tape and reel.

2. Waferanddieforthispart number is available which meets all elec­trical specifications. Pleasecontact your local sales office or Harris
customer service for ordering information.

August 1998

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.

Copyright

© Harris Corporation 1998

CD74AC251,

CD74ACT251

8-Input Multiplexer, Three-State

File Number 1981.1

2

Functional Diagram

TRUTH TABLE

INPUTS OUTPUTS

SELECT

OUTPUT ENABLE OE Y YS2 S1 S0

XXX H ZZ
LLL L I

0

I

0

LLH L I

1

I

1

LHL L I

2

I

2

LHH L I

3

I

3

HLL L I

4

I

4

HLH L I

5

I

5

HHL L I

6

I

6

HHH L I

7

I

7

H = High logic level,L=Lowlogic level,Z = High impedance (off),
X = Irrelevant, I0, I1...I7 = The level of the respective input

5

6

Y

Y

4
3

2
1

14

12

13

15

I

0

I

7

I

6

I

5

I

4

I

3

I

2

I

1

11

S

0

10

S

1

9

S

2

THREE-STATE

7

DISABLE OE

CHANNEL

INPUTS

DAT A

SELECT

OUTPUTS

CD74AC251, CD74ACT251

3

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC VCC or Ground Current, I

CC orIGND

(Note 3) . . . . . . . . .±100mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC (Note 4)

AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V

ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

CC

Input Rise and Fall Slew Rate, dt/dv

AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)

AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)

ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)

Thermal Resistance (Typical, Note 5) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ___

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ___

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

3. For up to 4 outputs per device, add ±25mA for each additional output.

4. Unless otherwise specified, all voltages are referenced to ground.

5. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

PARAMETER SYMBOL

TEST

CONDITIONS

V

CC

(V)

25oC

-40oC TO
85oC

-55oC TO
125oC

UNITSVI(V) IO(mA) MIN MAX MIN MAX MIN MAX

AC TYPES

High Level Input Voltage V

IH

- - 1.5 1.2 - 1.2 - 1.2 - V
3 2.1 - 2.1 - 2.1 - V

5.5 3.85 - 3.85 - 3.85 - V

Low Level Input Voltage V

IL

- - 1.5 - 0.3 - 0.3 - 0.3 V
3 - 0.9 - 0.9 - 0.9 V

5.5 - 1.65 - 1.65 - 1.65 V

High Level Output Voltage V

OH

VIH or V

IL

-0.05 1.5 1.4 - 1.4 - 1.4 - V

-0.05 3 2.9 - 2.9 - 2.9 - V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

-4 3 2.58 - 2.48 - 2.4 - V

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

(Note 6, 7)

5.5 - - 3.85 - - - V

-50

(Note 6, 7)

5.5----3.85 - V

CD74AC251, CD74ACT251

4

Low Level Output Voltage V

OL

VIH or V

IL

0.05 1.5 - 0.1 - 0.1 - 0.1 V

0.05 3 - 0.1 - 0.1 - 0.1 V

0.05 4.5 - 0.1 - 0.1 - 0.1 V
12 3 - 0.36 - 0.44 - 0.5 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75

(Note 6, 7)

5.5 - - - 1.65 - - V

50

(Note 6, 7)

5.5-----1.65 V

Input Leakage Current I

I

VCC or

GND

- 5.5 - ±0.1 - ±1-±1µA

Three-State Leakage
Current

I

OZ

VIH or V

IL

VO=V

CC

or GND

- 5.5 - ±0.5 - ±5-±10 µA

Quiescent Supply Current
MSI

I

CC

VCC or

GND

0 5.5 - 8 - 80 - 160 µA

ACT TYPES

High Level Input Voltage V

IH

- - 4.5 to

5.5

2-2-2-V

Low Level Input Voltage V

IL

- - 4.5 to

5.5

- 0.8 - 0.8 - 0.8 V

High Level Output Voltage V

OH

VIH or V

IL

-0.05 4.5 4.4 - 4.4 - 4.4 - V

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

(Note 6, 7)

5.5 - - 3.85 - - - V

-50

(Note 6, 7)

5.5----3.85 - V

Low Level Output Voltage V

OL

VIH or V

IL

0.05 4.5 - 0.1 - 0.1 - 0.1 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75

(Note 6, 7)

5.5 - - - 1.65 - - V

50

(Note 6, 7)

5.5-----1.65 V

Input Leakage Current I

I

VCC or

GND

- 5.5 - ±0.1 - ±1-±1µA

Three-State or Leakage
Current

I

OZ

VIH or V

IL

VO=V

CC

or GND

- 5.5 - ±0.5 - ±5-±10 µA

Quiescent Supply Current
MSI

I

CC

VCC or

GND

0 5.5 - 8 - 80 - 160 µA

AdditionalSupplyCurrent per
Input Pin TTL Inputs High
1 Unit Load

∆I

CC

V

CC

-2.1

- 4.5 to

5.5

- 2.4 - 2.8 - 3 mA

NOTES:

6. Test one output at a time fora 1-second maximum duration.Measurement is madeby forcing current andmeasuring voltage tominimize
power dissipation.

7. Test verifies a minimum 50Ω transmission-line-drive capability at 85oC, 75Ω at 125oC.

DC Electrical Specifications (Continued)

PARAMETER SYMBOL

TEST

CONDITIONS

V

CC

(V)

25oC

-40oC TO
85oC

-55oC TO
125oC

UNITSVI(V) IO(mA) MIN MAX MIN MAX MIN MAX

CD74AC251, CD74ACT251

5

ACT Input Load Table

INPUT UNIT LOAD

S0, S1, S3 1

OE 1

I0 - I

7

1

NOTE: Unit load is ∆ICClimit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.

Switching Specifications Input t

r

, tf = 3ns, CL= 50pF (Worst Case)

PARAMETER SYMBOL V

CC

(V)

-40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX

AC TYPES

Propagation Delay,
Data to Y Output

t

PLH

, t

PHL

1.5 - - 153 - - 169 ns

3.3

(Note 9)

4.9 - 17.2 4.7 - 18.9 ns

5

(Note 10)

3.5 - 12.3 3.4 - 13.5 ns

Propagation Delay,
Data to Y Output

t

PLH

, t

PHL

1.5 - - 169 - - 186 ns

3.3 5.4 - 19 5.2 - 20.9 ns
5 3.8 - 13.5 3.7 - 14.9 ns

Propagation Delay,
Select to Y Output

t

PLH

, t

PHL

1.5 - - 207 - - 228 ns

3.3 6.6 - 23.2 6.4 - 25.5 ns
5 4.7 - 16.5 4.6 - 18.2 ns

Propagation Delay,
Select to Y Output

t

PLH

, t

PHL

1.5 - - 223 - - 245 ns

3.3 7.1 - 24.9 6.9 - 27.4 ns
5 5.1 - 17.8 4.9 - 19.6 ns

Propagation Delay,
Output Enable and Output
Disable to Output

t

PZH

, t

PZL

,

t

PHZ

, t

PLZ

1.5 - - 155 - - 169 ns

3.3 5.2 - 18.7 5.1 - 20.3 ns
5 3.5 - 12.3 3.4 - 13.5 ns

Three-State Output
Capacitance

C

O

- - -15- -15pF

Input Capacitance C

I

- - -10- -10pF

Power Dissipation Capacitance C

PD

(Note 11)

- - 120 - - 120 - pF

ACT TYPES

Propagation Delay,
Data to Y Output

t

PLH

, t

PHL

5

(Note 10)

3.5 - 12.3 3.4 - 13.5 ns

Propagation Delay,
Data to Y Output

t

PLH

, t

PHL

5 3.8 - 13.5 3.7 - 14.9 ns

Propagation Delay,
Select to Y Output

t

PLH

, t

PHL

5 4.7 - 16.5 4.6 - 18.2 ns

Propagation Delay,
Select to Y Output

t

PLH

, t

PHL

5 5.1 - 17.8 4.9 - 19.6 ns

Propagation Delay,
Output Enable and Output
Disable to Output

t

PZH

, t

PZL

,

t

PHZ

, t

PLZ

5 3.5 - 12.3 3.4 - 13.5 ns

CD74AC251, CD74ACT251

6

Three-State Output
Capacitance

C

O

Input Capacitance C

I

- - -10- -10pF

Power Dissipation Capacitance C

PD

(Note 11)

- - 45 - - 45 - pF

NOTES:

8. Limits tested 100%.

9. 3.3V Min is at 3.6V, Max is at 3V.

10. 5V Min is at 5.5V, Max is at 4.5V.

11. CPD is used to determine the dynamic power consumption per device.
PD = V

CC

2

fi(CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

Switching Specifications Input t

r

, tf = 3ns, CL= 50pF (Worst Case) (Continued)

PARAMETER SYMBOL V

CC

(V)

-40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX

FIGURE 1. THREE-STATE PROPAGATION DELAY WAVEFORMS AND TEST CIRCUIT

FIGURE 2. PROPAGATION DELAY TIMES

DUT

WITH

THREE-

STATE

OUTPUT

INPUT LEVEL

90%
V

S

10%

GND

t

f

= 3ns

t

PZL

t

PZH

t

PLZ

t

PHZ

OUTPUTS
ENABLED

OUTPUTS

DISABLED

OUTPUT: LOW

TO OFF TO LOW

OUTPUT: HIGH

TO OFF TO HIGH

OTHER

INPUTS

(TIED HIGH

OR LOW)

OUTPUT

DISABLE

C

L

50pF

500Ω

†

R

L

500Ω†
R

L

OUT

V

S

0.2V

CC

VOL (≠ GND)

V

OH

(≠ VCC)

0.8 V

CC

V

S

GND (t

PHZ,tPZH

)

OUTPUTS
ENABLED

OPEN (t

PHL,tPLH

)

2 V

CC

(t

PLZ,tPZL

)

(OPEN DRAIN)

t

r

= 3ns

OUTPUT

DISABLE

†FOR AC SERIES ONLY: WHEN V

CC

= 1.5V, RL = 1kΩ

INPUT LEVEL

t

r

= 3ns tf = 3ns

90%

I

N

V

S

10%

V

S

V

S

t

PHL

t

PHL

t

PLH

INVERTING

OUTPUT

Y

NON-INVERTING

OUTPUT Y

t

PLH

CD74AC251, CD74ACT251

7

DUT

OUTPUT

R

L

(NOTE)

OUTPUT

LOAD

500Ω

C

L

50pF

NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.

FIGURE 3. PROPAGATION DELAY TIMES

CD74AC CD74ACT

Input Level V

CC

3V

Input Switching Voltage, V

S

0.5 V

CC

1.5V

Output Switching Voltage, V

S

0.5 V

CC

0.5 V

CC

CD74AC251, CD74ACT251

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