TEXAS INSTRUMENTS CD74AC251 Technical data

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CD74AC251,

Data sheet acquired from Harris Semiconductor
SCHS246

August 1998

Features

• Buffered Inputs

• Typical Propagation Delay

- 6ns at V

= 5V, TA = 25oC, CL = 50pF

CC

• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015

• SCR-Latchup-Resistant CMOS Process and Circuit
Design

• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption

• Balanced Propagation Delays

• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply

• ±24mA Output Drive Current

- Fanout to 15 FAST™ ICs

- Drives 50Ω Transmission Lines

Pinout

CD74AC251, CD74ACT251

(PDIP, SOIC)

TOP VIEW

V

16

CC

I

15

4

14

I

5

13

I

6

12

I

7

11

S0

10

S1
S2

9

OE

GND

1

I

3

2

I

2

3

I

1

4

I

0

5

Y

6

Y

7
8

CD74ACT251

8-Input Multiplexer, Three-State

Description

The CD74AC251 and CD74ACT251 8-input multiplexers that
utilize the Harris Advanced CMOS Logic technology. This
multiplexerfeatures both true (Y) and complement (
as well as an Output Enable (

OE) input. The OE must be at a
LOW logic level to enable this device. When the
HIGH, both outputs are in the high-impedance state. When
enabled, address inf ormation on the data select inputs deter­mines which data input is routed to the Y and

Ordering Information

PART

NUMBER

CD74AC251E 0 to 70oC, -40 to 85,

CD74ACT251E 0 to 70oC, -40 to 85,

CD74AC251M 0 to 70oC, -40 to 85,

CD74ACT251M 0 to 70oC, -40 to 85,

NOTES:

1. When ordering, usethe entire part number.Add the suffix 96to
obtain the variant in the tape and reel.

2. Waferanddieforthispart number is available which meets all elec­trical specifications. Pleasecontact your local salesoffice or Harris
customer service for ordering information.

TEMP.

RANGE (oC) PACKAGE

16 Ld PDIP E16.3

-55 to 125
16 Ld PDIP E16.3

-55 to 125
16 Ld SOIC M16.15

-55 to 125
16 Ld SOIC M16.15

-55 to 125

Y) outputs

OE input is

Y outputs.

PKG.

NO.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.

Copyright

© Harris Corporation 1998

1

File Number 1981.1

CD74AC251, CD74ACT251

Functional Diagram

THREE-STATE

DISABLE OE

I

0

I

1

I

2

I

CHANNEL

INPUTS

DAT A

SELECT

3

15

I

4

14

I

5

13

I

6

12

I

7

11

S

0

10

S

1

S

2

TRUTH TABLE

INPUTS OUTPUTS

SELECT

OUTPUT ENABLE OE Y YS2 S1 S0

XXX H ZZ
LLL L I
LLH L I
LHL L I
LHH L I
HLL L I
HLH L I
HHL L I
HHH L I

H = High logic level,L=Lowlogic level,Z = High impedance (off),
X = Irrelevant, I0, I1...I7 = The level of the respective input

7

4
3

2
1

5

Y

OUTPUTS

6

Y

9

I

0

I

1

I

2

I

3

I

4

I

5

I

6

I

7

0
1
2
3
4
5
6
7

2

CD74AC251, CD74ACT251

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V

DC Input Diode Current, I

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC Output Source or Sink Current per Output Pin, I

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC VCC or Ground Current, I

IK

OK

CC orIGND

O

(Note 3) . . . . . . . . .±100mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC (Note 4)

AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V

ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Slew Rate, dt/dv

AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)

AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)

ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

3. For up to 4 outputs per device, add ±25mA for each additional output.

4. Unless otherwise specified, all voltages are referenced to ground.

5. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 5) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ___

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ___

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

CC

DC Electrical Specifications

PARAMETER SYMBOL

AC TYPES

High Level Input Voltage V

Low Level Input Voltage V

High Level Output Voltage V

IH

IL

OH

TEST

CONDITIONS

- - 1.5 1.2 - 1.2 - 1.2 - V

- - 1.5 - 0.3 - 0.3 - 0.3 V

VIH or V

-0.05 1.5 1.4 - 1.4 - 1.4 - V

IL

-0.05 3 2.9 - 2.9 - 2.9 - V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

-4 3 2.58 - 2.48 - 2.4 - V

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

(Note 6, 7)

-50

(Note 6, 7)

V

CC

(V)

3 2.1 - 2.1 - 2.1 - V

5.5 3.85 - 3.85 - 3.85 - V

3 - 0.9 - 0.9 - 0.9 V

5.5 - 1.65 - 1.65 - 1.65 V

5.5 - - 3.85 - - - V

5.5----3.85 - V

25oC

-40oC TO
85oC

-55oC TO
125oC

UNITSVI(V) IO(mA) MIN MAX MIN MAX MIN MAX

3

CD74AC251, CD74ACT251

DC Electrical Specifications (Continued)

-40oC TO
85oC

PARAMETER SYMBOL

Low Level Output Voltage V

OL

CONDITIONS

VIH or V

TEST

V

CC

25oC

(V)

0.05 1.5 - 0.1 - 0.1 - 0.1 V

IL

0.05 3 - 0.1 - 0.1 - 0.1 V

0.05 4.5 - 0.1 - 0.1 - 0.1 V
12 3 - 0.36 - 0.44 - 0.5 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75

5.5 - - - 1.65 - - V

(Note 6, 7)

50

5.5-----1.65 V

(Note 6, 7)

Input Leakage Current I

I

VCC or

- 5.5 - ±0.1 - ±1-±1µA

GND

Three-State Leakage
Current

I

OZ

VIH or V
VO=V

CC

IL

- 5.5 - ±0.5 - ±5-±10 µA

or GND

Quiescent Supply Current
MSI

I

CC

VCC or

0 5.5 - 8 - 80 - 160 µA

GND

ACT TYPES

High Level Input Voltage V

IH

- - 4.5 to

2-2-2-V

5.5

Low Level Input Voltage V

IL

- - 4.5 to

- 0.8 - 0.8 - 0.8 V

5.5

High Level Output Voltage V

OH

VIH or V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

IL

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

5.5 - - 3.85 - - - V

(Note 6, 7)

-50

5.5----3.85 - V

(Note 6, 7)

Low Level Output Voltage V

OL

VIH or V

0.05 4.5 - 0.1 - 0.1 - 0.1 V

IL

24 4.5 - 0.36 - 0.44 - 0.5 V
75

5.5 - - - 1.65 - - V

(Note 6, 7)

50

5.5-----1.65 V

(Note 6, 7)

Input Leakage Current I

I

VCC or

- 5.5 - ±0.1 - ±1-±1µA

GND

Three-State or Leakage
Current

I

OZ

VIH or V
VO=V

CC

IL

- 5.5 - ±0.5 - ±5-±10 µA

or GND

Quiescent Supply Current
MSI

AdditionalSupplyCurrentper
Input Pin TTL Inputs High

I

CC

VCC or

0 5.5 - 8 - 80 - 160 µA

GND

∆I

CC

V

-2.1

CC

- 4.5 to

5.5

- 2.4 - 2.8 - 3 mA

1 Unit Load

NOTES:

6. Test one output at a time fora 1-secondmaximum duration.Measurement ismade byforcing currentand measuringvoltage tominimize
power dissipation.

7. Test verifies a minimum 50Ω transmission-line-drive capability at 85oC, 75Ω at 125oC.

-55oC TO
125oC

UNITSVI(V) IO(mA) MIN MAX MIN MAX MIN MAX

4

CD74AC251, CD74ACT251

ACT Input Load Table

INPUT UNIT LOAD

S0, S1, S3 1

OE 1

I0 - I

7

NOTE: Unit load is ∆ICClimit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.

1

Switching Specifications Input t

PARAMETER SYMBOL V

AC TYPES

Propagation Delay,
Data to Y Output

Propagation Delay,
Data to Y Output

Propagation Delay,
Select to Y Output

Propagation Delay,
Select to Y Output

Propagation Delay,
Output Enable and Output
Disable to Output

Three-State Output
Capacitance

Input Capacitance C
Power Dissipation Capacitance C

ACT TYPES

Propagation Delay,
Data to Y Output

Propagation Delay,
Data to Y Output

Propagation Delay,
Select to Y Output

Propagation Delay,
Select to Y Output

Propagation Delay,
Output Enable and Output
Disable to Output

t

PLH

t

PLH

t

PLH

t

PLH

t

PZH

t

PHZ

(Note 11)

t

PLH

t

PLH

t

PLH

t

PLH

t

PZH

t

PHZ

, tf = 3ns, CL= 50pF (Worst Case)

r

(V)

CC

, t

PHL

1.5 - - 153 - - 169 ns

3.3

4.9 - 17.2 4.7 - 18.9 ns

(Note 9)

5

3.5 - 12.3 3.4 - 13.5 ns

(Note 10)

, t

PHL

1.5 - - 169 - - 186 ns

3.3 5.4 - 19 5.2 - 20.9 ns
5 3.8 - 13.5 3.7 - 14.9 ns

, t

PHL

1.5 - - 207 - - 228 ns

3.3 6.6 - 23.2 6.4 - 25.5 ns
5 4.7 - 16.5 4.6 - 18.2 ns

, t

PHL

1.5 - - 223 - - 245 ns

3.3 7.1 - 24.9 6.9 - 27.4 ns
5 5.1 - 17.8 4.9 - 19.6 ns

, t

,

PZL

, t

PLZ

1.5 - - 155 - - 169 ns

3.3 5.2 - 18.7 5.1 - 20.3 ns
5 3.5 - 12.3 3.4 - 13.5 ns

C

O

I

PD

, t

PHL

- - -15- -15pF

- - -10- -10pF

- - 120 - - 120 - pF

5

3.5 - 12.3 3.4 - 13.5 ns

(Note 10)

, t

PHL

, t

PHL

, t

PHL

, t

,

PZL

, t

PLZ

5 3.8 - 13.5 3.7 - 14.9 ns

5 4.7 - 16.5 4.6 - 18.2 ns

5 5.1 - 17.8 4.9 - 19.6 ns

5 3.5 - 12.3 3.4 - 13.5 ns

-40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX

5

CD74AC251, CD74ACT251

Switching Specifications Input t

PARAMETER SYMBOL V

Three-State Output

, tf = 3ns, CL= 50pF (Worst Case) (Continued)

r

(V)

CC

C

O

Capacitance
Input Capacitance C
Power Dissipation Capacitance C

I

PD

- - -10- -10pF

- - 45 - - 45 - pF

(Note 11)

NOTES:

8. Limits tested 100%.

9. 3.3V Min is at 3.6V, Max is at 3V.

10. 5V Min is at 5.5V, Max is at 4.5V.

11. CPD is used to determine the dynamic power consumption per device.
PD = V

2

fi(CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

CC

t

= 3ns

r

OUTPUT

DISABLE

t

PLZ

OUTPUT: LOW

TO OFF TO LOW

t

PHZ

OUTPUT: HIGH

TO OFF TO HIGH

OUTPUTS
ENABLED

OTHER

INPUTS

(TIED HIGH

OR LOW)

OUTPUT

DISABLE

DUT

WITH

THREE-

STATE

OUTPUT

†FOR AC SERIES ONLY: WHEN V

OUTPUTS

DISABLED

C
50pF

= 1.5V, RL = 1kΩ

CC

-40oC TO 85oC -55oC TO 125oC

= 3ns

t

L

f

t

PZL

t

PZH

500Ω
R

L

†

500Ω†
R

L

INPUT LEVEL

GND

V

S

0.2V

CC

VOL (≠ GND)

V

0.8 V

CC

V

S

OUTPUTS
ENABLED

GND (t

PHZ,tPZH

OPEN (t

PHL,tPLH

(t

2 V

CC

PLZ,tPZL

(OPEN DRAIN)

OUT

OH

90%
V

S

10%

(≠ VCC)

)

)

)

UNITSMIN TYP MAX MIN TYP MAX

FIGURE 1. THREE-STATE PROPAGATION DELAY WAVEFORMS AND TEST CIRCUIT

= 3ns tf = 3ns

t

r

90%

I

N

V

S

10%

INVERTING

OUTPUT

NON-INVERTING

Y

t

PHL

OUTPUT Y

t

PLH

t

t

PLH

PHL

INPUT LEVEL

V

S

V

S

FIGURE 2. PROPAGATION DELAY TIMES

6

DUT

OUTPUT

R

L

CD74AC251, CD74ACT251

(NOTE)
500Ω

OUTPUT

LOAD

C

L

50pF

NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.

CD74AC CD74ACT

Input Level V
Input Switching Voltage, V
Output Switching Voltage, V

S

S

0.5 V

0.5 V

CC

CC
CC

FIGURE 3. PROPAGATION DELAY TIMES

3V

1.5V

0.5 V

CC

7

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