TEXAS INSTRUMENTS CD74AC245 Technical data

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CD74AC245,

[ /Title
(CD74
AC245
,
CD74
ACT24

5)
/Sub­ject
(Octal­Bus
Trans­ceiver,
Three­State,
Non­Invert­ing)
/Autho
r ()
/Key­words
(Har­ris
Semi­con­ductor,
Advan
ced
CMOS
,Harris
Semi­con-

Data sheet acquired from Harris Semiconductor
SCHS245

September 1998

Features

• Buffered Inputs

• Typical Propagation Delay

- 4ns at V

• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015

• SCR-Latchup-Resistant CMOS Process and Circuit
Design

• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption

• Balanced Propagation Delays

• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply

• ±24mA Output Drive Current

- Fanout to 15 FAST™ ICs

- Drives 50Ω Transmission Lines

= 5V, TA = 25oC, CL = 50pF

CC

Pinout

DIR

A0
A1
A2
A3
A4
A5
A6
A7

GND

Description

The CD74AC245 and CD74ACT245 are octal-bus transceiv­ers that utilize the Harris Advanced CMOS Logic technology.
They are non-inverting three-state bidirectional transceiver­buffers intendedfor two-way transmission from “A” bus to “B”
bus or “B” bus to “A”. The logic level present on the direction
input (DIR) determines the data direction. When the output
enable input (
impedance state.

Ordering Information

PART

NUMBER

CD74AC245E -55 to 125 20 Ld PDIP E20.3
CD74ACT245E -55 to 125 20 Ld PDIP E20.3
CD74AC245M -55 to 125 20 Ld SOIC M20.3
CD74ACT245M -55 to 125 20 Ld SOIC M20.3
CD74AC245SM -55 to 125 20 Ld SSOP M20.15
CD74ACT245SM -55 to 125 20 Ld SSOP M20.15

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer and die for this part number is availablewhichmeetsallelec­trical specifications. Please contact your local sales office or Harris
customer service for ordering information.

CD74AC245, CD74ACT245

(PDIP, SSOP, SOIC)

TOP VIEW

1
2
3
4
5
6
7
8
9

10

V

20

CC

OE

19

B0

18

B1

17

B2

16

B3

15

B4

14

B5

13
12

B6
B7

11

CD74ACT245

Octal-Bus Transceiver,

Three-State, Non-Inverting

OE) is HIGH, the outputs are in the high-

TEMP.

RANGE (oC) PACKAGE

PKG.

NO.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.

Copyright

© Harris Corporation 1998

1

File Number 1907.1

Functional Diagram

CD74AC245, CD74ACT245

A0

A1

A2

A3

A4

A5

A6

A7

DIR

OE

2

3

4

5

6

7

8

9

1

19

18

B0

17

B1

16

B2

15

B3

14

B4

13

B5

12

B6

11

B7

TRUTH TABLE

CONTROL INPUTS

OPERATIONOE DIR

L L B Data to A Bus
L H A Data to B Bus

H X Isolation

H = High Level, L = Low Level, X = Irrelevant
To prevent excess currents in the High-Z (isolation) modes, all I/O
terminals should be terminated with 10kΩ to 1MΩ resistors.

2

CD74AC245, CD74ACT245

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V

DC Input Diode Current, I

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC Output Source or Sink Current per Output Pin, I

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC VCC or Ground Current, I

IK

OK

CC orIGND

O

(Note 3) . . . . . . . . .±100mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC (Note 4)

AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V

ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Slew Rate, dt/dv

AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)

AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)

ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

3. For up to 4 outputs per device, add ±25mA for each additional output.

4. Unless otherwise specified, all voltages are referenced to ground.

5. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 5) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

CC

DC Electrical Specifications

PARAMETER SYMBOL

AC TYPES

High Level Input Voltage V

Low Level Input Voltage V

High Level Output Voltage V

IH

IL

OH

TEST

CONDITIONS

- - 1.5 1.2 - 1.2 - 1.2 - V

- - 1.5 - 0.3 - 0.3 - 0.3 V

VIH or V

-0.05 1.5 1.4 - 1.4 - 1.4 - V

IL

-0.05 3 2.9 - 2.9 - 2.9 - V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

-4 3 2.58 - 2.48 - 2.4 - V

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

(Note 6, 7)

-50

(Note 6, 7)

V

CC

(V)

3 2.1 - 2.1 - 2.1 - V

5.5 3.85 - 3.85 - 3.85 - V

3 - 0.9 - 0.9 - 0.9 V

5.5 - 1.65 - 1.65 - 1.65 V

5.5 - - 3.85 - - - V

5.5----3.85 - V

25oC

-40oC TO
85oC

-55oC TO
125oC

UNITSVI(V) IO(mA) MIN MAX MIN MAX MIN MAX

3

CD74AC245, CD74ACT245

DC Electrical Specifications (Continued)

-40oC TO
85oC

PARAMETER SYMBOL

Low Level Output Voltage V

OL

CONDITIONS

VIH or V

TEST

V

CC

25oC

(V)

0.05 1.5 - 0.1 - 0.1 - 0.1 V

IL

0.05 3 - 0.1 - 0.1 - 0.1 V

0.05 4.5 - 0.1 - 0.1 - 0.1 V
12 3 - 0.36 - 0.44 - 0.5 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75

5.5 - - - 1.65 - - V

(Note 6, 7)

50

5.5-----1.65 V

(Note 6, 7)

Input Leakage Current I

I

VCC or

- 5.5 - ±0.1 - ±1-±1µA

GND

Three-State Leakage
Current

I

OZ

VIH or V
VO=V

CC

IL

- 5.5 - ±0.5 - ±5-±10 µA

or GND

Quiescent Supply Current
MSI

I

CC

VCC or

0 5.5 - 8 - 80 - 160 µA

GND

ACT TYPES

High Level Input Voltage V

IH

- - 4.5 to

2-2-2-V

5.5

Low Level Input Voltage V

IL

- - 4.5 to

- 0.8 - 0.8 - 0.8 V

5.5

High Level Output Voltage V

OH

VIH or V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

IL

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

5.5 - - 3.85 - - - V

(Note 6, 7)

-50

5.5----3.85 - V

(Note 6, 7)

Low Level Output Voltage V

OL

VIH or V

0.05 4.5 - 0.1 - 0.1 - 0.1 V

IL

24 4.5 - 0.36 - 0.44 - 0.5 V
75

5.5 - - - 1.65 - - V

(Note 6, 7)

50

5.5-----1.65 V

(Note 6, 7)

Input Leakage Current I

I

VCC or

- 5.5 - ±0.1 - ±1-±1µA

GND

Three-State or Leakage
Current

I

OZ

VIH or V
VO=V

CC

IL

- 5.5 - ±0.5 - ±5-±10 µA

or GND

Quiescent Supply Current
MSI

AdditionalSupplyCurrent per
Input Pin TTL Inputs High

I

CC

VCC or

0 5.5 - 8 - 80 - 160 µA

GND

∆I

CC

V

-2.1

CC

- 4.5 to

5.5

- 2.4 - 2.8 - 3 mA

1 Unit Load

NOTES:

6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.

7. Test verifies a minimum 50Ω transmission-line-drive capability at 85oC, 75Ω at 125oC.

-55oC TO
125oC

UNITSVI(V) IO(mA) MIN MAX MIN MAX MIN MAX

4

CD74AC245, CD74ACT245

ACT Input Load Table

INPUT UNIT LOAD

An, Bn 0.83

OE 0.64

DIR 0.15

NOTE: Unit load is ∆ICClimit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.

Switching Specifications Input t

PARAMETER SYMBOL VCC (V)

AC TYPES

Propagation Delay,
Data to Output

Propagation Delay,
Output Disable to Output

Propagation Delay,
Output Enable to Output

Minimum (Valley) V
Switching of Other Outputs
(Output Under Test Not Switching)

Maximum (Peak) V
Switching of Other Outputs
(Output Under Test Not Switching)

OH

OL

During

See Figure 1

During

See Figure 1

, tf = 3ns, CL= 50pF (Worst Case)

r

t

PLH

, t

PHL

1.5 - - 96 - - 106 ns

3.3

3.2 - 10.8 3 - 11.9 ns

(Note 9)

5

2.2 - 7.7 2.1 - 8.5 ns

(Note 10)

t

PLZ

, t

PHZ

1.5 - - 159 - - 175 ns

3.3 4.7 - 15.9 4.4 - 17.5 ns
5 3.7 - 12.7 3.5 - 14 ns

t

PZL

, t

PZH

1.5 - - 159 - - 175 ns

3.3 5.6 - 19 5.3 - 21 ns
5 3.7 - 12.7 3.5 - 14 ns

V

V

OHV

OLP

5 - 4 at

5 - 1 at

o

C TO 85oC -55oC TO 125oC

-40

- - 4 at

25oC

25oC

- - 1 at

25oC

25oC

UNITSMIN TYP MAX MIN TYP MAX

-V

-V

Three-State Output Capacitance C
Input Capacitance C
Power Dissipation Capacitance C

(Note 11)

ACT TYPES

Propagation Delay,

t

PLH

Data to Output
Propagation Delay,

t

PLZ

Output Disable to Output
Propagation Delay,

Output Enable to Output
Minimum (Valley) V

OH

During

Switching of Other Outputs

t

PZL

V

See Figure 1

(Output Under Test Not Switching)
Maximum (Peak) V

OL

During

Switching of Other Outputs

V

See Figure 1

(Output Under Test Not Switching)

O

I

PD

, t

, t

, t

OHV

OLP

PHL

PHZ

PZH

- - 15 - - 15 - pF

- - -10- -10pF

- - 57 - - 57 - pF

5

2.7 - 9.1 2.5 - 10 ns

(Note 10)

5 3.7 12.7 3.5 14 ns

5 3.8 13.1 3.6 14.4 ns

5 - 4 at

25oC

5 - 1 at

25oC

- - 4 at
25oC

- - 1 at
25oC

-V

-V

5

CD74AC245, CD74ACT245

Switching Specifications Input t

r

PARAMETER SYMBOL VCC (V)

Three-State Output Capacitance C
Input Capacitance C
Power Dissipation Capacitance C

(Note 11)

NOTES:

8. Limits tested 100%.

9. 3.3V Min is at 3.6V, Max is at 3V.

10. 5V Min is at 5.5V, Max is at 4.5V

11. C

is used to determine the dynamic power consumption per channel.

PD

AC: PD = V
ACT: PD = V

2

fi(CPD + CL)

CC

2

fi(CPD + CL) + VCC∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

CC

OTHER
OUTPUTS

OUTPUT
UNDER
TEST

, tf = 3ns, CL= 50pF (Worst Case) (Continued)

o

C TO 85oC -55oC TO 125oC

-40

O

I

PD

- - 15 - - 15 - pF

- - -10- -10pF

- - 57 - - 57 - pF

V

V

V
V

V
V

UNITSMIN TYP MAX MIN TYP MAX

OH

OL

OH
OHV

OLP
OL

NOTES:

12. Input pulses have the following characteristics: PRR ≤ 1MHz, t

= 3ns, SKEW 1ns.

r

13. R.F. fixture with 700MHz design rules required. IC should be soldered into test board and bypassed with 0.1µF capacitor. Scope and
probes require 700MHz bandwidth.

FIGURE 1. SIMULTANEOUS SWITCHING TRANSIENT WAVEFORMS

6

OUTPUTS

DISABLED

OUTPUT:

LOW TO OFF

TO LOW

OUTPUT:

HIGH TO OFF

TO HIGH

t

= 3ns

f

CD74AC245, CD74ACT245

t

= 3ns

r

t

PLZ

t

OUTPUTS
ENABLED

PHZ

DISABLED

OUTPUTS

t

PZL

t

PZH

INPUT LEVEL

GND

V

S

0.2 V

CC

0.8 V

CC

V

S

OUTPUTS
ENABLED

90%
V

S

10%

VOL (≠ VCC)

OTHER

INPUTS

TIED HIGH

OR LOW

OUTPUT

DISABLE

NOTE:

14. For AC Series only: When VCC = 1.5V, RL = 1kΩ.

FIGURE 2. THREE-STATE PROPAGATION DELAY TIMES AND TEST CIRCUIT

INPUT
LEVEL

An

GND

t

PLH

Bn

FIGURE 3. PROPAGATION DELAY TIMES

DUT WITH

THREE-

STATE

OUTPUT

tr = 3ns

C

L

50pF

R

L

500Ω

R
500Ω

(NOTE 14)

GND (t

OPEN (t

2 VCC (t
(OPEN DRAIN)

L

OUT

PHZ

, t

PHL

PLZ

, t

tf = 3ns

PZH

, t

t

PHL

PLH

PZL

)

90%
V

S

10%

V

S

)

)

OUTPUT

R

(NOTE)

L

C

L

50pF

500Ω

DUT

OUTPUT

LOAD

NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.

CD74AC CD74ACT

Input Level V
Input Switching Voltage, V
Output Switching Voltage, V

S

S

0.5 V

0.5 V

CC

CC
CC

FIGURE 4. PROPAGATION DELAY TIMES

3V

1.5V

0.5 V

CC

7

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