TEXAS INSTRUMENTS CD74AC175 Technical data

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CD74AC175,

[ /Title
(CD74
AC175
,
CD74
ACT17
5
)

Sub-

ect
(Quad
D Flip­Flop
with
Reset)

Autho
r ()

Key­words
(Har­ris
Semi­con­ductor,
Advan
ced
CMOS
,Harris
Semi­con­ductor,
Advan
ced
TTL)

Cre­ator ()

DOCI
NFO

Data sheet acquired from Harris Semiconductor
SCHS242

September 1998

Features

• Buffered Inputs

• Typical Propagation Delay

- 6.4ns at V

• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015

• SCR-Latchup-Resistant CMOS Process and Circuit
Design

• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption

• Balanced Propagation Delays

• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply

• ±24mA Output Drive Current

- Fanout to 15 FAST™ ICs

- Drives 50Ω Transmission Lines

= 5V, TA = 25oC, CL = 50pF

CC

Pinout

MR

Q0
Q0
D0
D1
Q1
Q1

GND

Description

The CD74AC175 and CD74ACT175 are quad D flip-flops
with reset that utilize the Harris Advanced CMOS Logic tech­nology. Information at the D input is transferred to the Q and
Q outputs on the positive-going edge of the clock pulse. All
four flip-flops are controlled by a common clock (CP) and a
common reset (
logic level independent of the clock.

Ordering Information

PART

NUMBER

CD74AC175E -55 to 125 16 Ld PDIP E16.3
CD74ACT175E -55 to 125 16 Ld PDIP E16.3
CD74AC175M -55 to 125 16 Ld SOIC M16.15
CD74ACT175M -55 to 125 16 Ld SOIC M16.15

NOTES:

13. Whenordering,use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

14. Waferand die for this part number is available which meets all elec­trical specifications. Please contact your local sales office or Harris
customer service for ordering information.

CD74AC175, CD74ACT175

(PDIP, SOIC)

TOP VIEW

V

1
2
3
4
5
6
7
8

16

CC

Q3

15
14

Q3

13

D3

12

D2

11

Q2

10

Q2
CP

9

CD74ACT175

Quad D Flip-Flop with Reset

MR). Resetting is accomplished by a LOW

TEMP.

RANGE (oC) PACKAGE

PKG.

NO.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.

Copyright

© Harris Corporation 1998

1

File Number 1964.1

Functional Diagram

CD74AC175, CD74ACT175

D0
CP

MR

D1

D2

D3

GND = 8

V

= 16

CC

4
9
1

5

12

13

D
CP
R

D
CP
R

D
CP
R

D
CP
R

2

Q

Q0

3

Q

Q0

7

Q

Q1

6

Q

Q1

10

Q

Q2

11

Q

Q2

15

Q

Q3

14

Q

Q3

TRUTH TABLE (EACH FLIP-FLOP)

INPUTS OUTPUTS

RESET

(MR)

CLOCK

CP

DATA

Dn Qn Qn

LXXLH
H↑HHL
H↑LLH
HLXQ0Q0

H = High Level (Steady State)
L = Low Level (Steady State)
X = Irrelevant
↑ = Transition from Low to High level
Q0, Q0 = Levelbefore the Indicated Steady-State Input conditions
were established.

2

CD74AC175, CD74ACT175

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC VCC or Ground Current, I

CC orIGND

(Note 3) . . . . . . . . .±100mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC (Note 4)

AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V

ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Slew Rate, dt/dv

AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)

AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)

ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

15. For up to 4 outputs per device, add ±25mA for each additional output.

16. Unless otherwise specified, all voltages are referenced to ground.

17. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 5) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Maximum Junction Temperature (Plastic Package) . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

AC TYPES

High Level Input Voltage V

Low Level Input Voltage V

High Level Output Voltage V

IH

IL

OH

TEST

CONDITIONS

(V) IO(mA) MIN MAX MIN MAX MIN MAX

I

V

CC

(V)

25

o

C

-40oC TO
85oC

-55oC TO
125oC

- - 1.5 1.2 - 1.2 - 1.2 - V
3 2.1 - 2.1 - 2.1 - V

5.5 3.85 - 3.85 - 3.85 - V

- - 1.5 - 0.3 - 0.3 - 0.3 V
3 - 0.9 - 0.9 - 0.9 V

5.5 - 1.65 - 1.65 - 1.65 V

VIH or V

-0.05 1.5 1.4 - 1.4 - 1.4 - V

IL

-0.05 3 2.9 - 2.9 - 2.9 - V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

-4 3 2.58 - 2.48 - 2.4 - V

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

5.5 - - 3.85 - - - V

(Note 6, 7)

-50

5.5----3.85 - V

(Note 6, 7)

UNITSV

3

CD74AC175, CD74ACT175

DC Electrical Specifications (Continued)

PARAMETER SYMBOL

Low Level Output Voltage V

OL

TEST

CONDITIONS

(V) IO(mA) MIN MAX MIN MAX MIN MAX

I

VIH or V

0.05 1.5 - 0.1 - 0.1 - 0.1 V

IL

V

CC

(V)

25

o

C

0.05 3 - 0.1 - 0.1 - 0.1 V

0.05 4.5 - 0.1 - 0.1 - 0.1 V
12 3 - 0.36 - 0.44 - 0.5 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75

5.5 - - - 1.65 - - V

(Note 6, 7)

50

5.5-----1.65 V

(Note 6, 7)

Input Leakage Current I

I

VCC or

- 5.5 - ±0.1 - ±1-±1µA

GND

Quiescent Supply Current
MSI

I

CC

VCC or

GND

0 5.5 - 8 - 80 - 160 µA

ACT TYPES

High Level Input Voltage V

IH

- - 4.5 to

2-2-2-V

5.5

Low Level Input Voltage V

IL

- - 4.5 to

- 0.8 - 0.8 - 0.8 V

5.5

High Level Output Voltage V

OH

VIH or V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

IL

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

5.5 - - 3.85 - - - V

(Note 6, 7)

-50

5.5----3.85 - V

(Note 6, 7)

Low Level Output Voltage V

OL

VIH or V

0.05 4.5 - 0.1 - 0.1 - 0.1 V

IL

24 4.5 - 0.36 - 0.44 - 0.5 V
75

5.5 - - - 1.65 - - V

(Note 6, 7)

50

5.5-----1.65 V

(Note 6, 7)

Input Leakage Current I

I

VCC or

- 5.5 - ±0.1 - ±1-±1µA

GND

Quiescent Supply Current
MSI

AdditionalSupply Current per
Input Pin TTL Inputs High

I

CC

VCC or

GND

∆I

CC

V

CC

-2.1

0 5.5 - 8 - 80 - 160 µA

- 4.5 to

- 2.4 - 2.8 - 3 mA

5.5

1 Unit Load

NOTES:

18. Testone output at a time for a1-second maximumduration. Measurementis made by forcing current and measuring voltage tominimize
power dissipation.

o

19. Test verifies a minimum 50Ω transmission-line-drive capability at 85

C, 75Ω at 125oC.

-40oC TO
85oC

-55oC TO
125oC

UNITSV

ACT Input Load Table

INPUT UNIT LOAD

Dn 0.58
MR 0.67
CP 0.92

NOTE: Unitload is ∆ICClimit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.

4

CD74AC175, CD74ACT175

Prerequisite For Switching Function

PARAMETER SYMBOL VCC (V)

AC TYPES

Data to CP Set-Up Time t

Hold Time t

Removal Time, MR to CP t

MR Pulse Width t

CP Pulse Width t

CP Frequency f

ACT TYPES

Data to CP Set-Up Time t

Hold Time t
Removal Time, MR to CP t
MR Pulse Width t
Clock Pulse Width t
CP Frequency f

NOTES:

20. 3.3V Min is at 3V.

21. 5V Min is at 4.5V.

SU

H

REM

W

W

MAX

SU

H

REM

W
W

MAX

-40oC TO 85oC -55oC TO 125oC
UNITSMIN MAX MIN MAX

1.5 2 - 2 - ns

3.3

2-2-ns

(Note 8)

5

2-2-ns

(Note 9)

1.5 2 - 2 - ns

3.3 2 - 2 - ns
52-2-ns

1.5 1 - 1 - ns

3.3 1 - 1 - ns
51-1-ns

1.5 44 - 50 - ns

3.3 4.9 - 5.6 - ns
5 3.5 - 4 - ns

1.5 55 - 63 - ns

3.3 6.1 - 7 - ns
5 4.4 - 5 - ns

1.5 9 - 8 - MHz

3.3 81 - 71 - MHz
5 114 - 100 - MHz

5

2-2-ns

(Note 9)

52-2-ns
51-1-ns
5 3.5 - 4 - ns
5 4.4 - 5 - ns
5 114 - 114 - MHz

Switching Specifications Input t

PARAMETER SYMBOL VCC (V)

AC TYPES

Propagation Delay, CP to Q,

Qt

PLH

, tf = 3ns, CL= 50pF (Worst Case)

r

, t

PHL

1.5 - - 139 - - 153 ns

3.3

4.4 - 15.5 4.3 - 17.1 ns

(Note 11)

5

3.2 - 11.1 3.1 - 12.2 ns

(Note 12)

5

o

-40

C TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN TYP MAX

CD74AC175, CD74ACT175

Switching Specifications Input t

PARAMETER SYMBOL VCC (V)

Propagation Delay, MR to Q, Qt

Input Capacitance C
Power Dissipation Capacitance C

ACT TYPES

Propagation Delay, CP to Qn t

Propagation Delay,

MR to Qn t
Input Capacitance C
Power Dissipation Capacitance C

NOTES:

22. Limits tested 100%.

23. 3.3V Min is at 3.6V, Max is at 3V.

24. 5V Min is at 5.5V, Max is at 4.5V.

25. C

is used to determine the dynamic power consumption per flip-flop.

PD

PD=CPDV

2

fi+ Σ (CL+VCC2fo)+VCC∆ICCwhere fi= input frequency, fo= output frequency, CL= output load capacitance, VCC=

CC

supply voltage.

PLH

(Note 13)

PLH

PLH

(Note 13)

, tf = 3ns, CL= 50pF (Worst Case) (Continued)

r

o

-40

C TO 85oC -55oC TO 125oC

, t

PHL

1.5 - - 139 - - 153 ns

3.3 4.4 - 15.5 4.3 - 17.1 ns
5 3.2 - 11.1 3.1 - 12.2 ns

- - -10- -10pF

- - 55 - - 55 - pF

5

3 - 10.5 2.9 - 11.5 ns

PD

, t

I

PHL

(Note 12)

, t

PD

PHL

I

5 3.3 - 11.8 3.3 - 13 ns

- - -10- -10pF

- - 55 - - 55 - pF

UNITSMIN TYP MAX MIN TYP MAX

INPUT LEVEL

GND

INPUT LEVEL

GND

INPUT LEVEL

GND

CP

INPUT LEVEL

GND

INPUT

V

S

t

PHL

V

t

S

W

V

S

t

V

S

PLH

V

S

MR

V

S

CP

t

PHL

Q

Q

V

S

t

W

V

S

t

REM

V

S

FIGURE 5. PROPAGATION DELAYS FIGURE 6. RESET OR SET PREREQUISITE AND

PROPAGATION DELAYS

OUTPUT

R

(NOTE)

L

500Ω

C

L

50pF

CD74AC CD74ACT

CC

0.5 V

CC

0.5 V

CC

CP

DUT

OUTPUT

D

V

S

tSU(L)

V

S

V

S

V

S

(L)

t

H

t

SU

(H)

V

S

tH(H)

V

S

NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.

LOAD

Input Level V
Input Switching Voltage, V
Output Switching Voltage, V

S

S

3V

1.5V

0.5 V

CC

FIGURE 7. FIGURE 8. PROPAGATION DELAY TIMES

6

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