TEXAS INSTRUMENTS CD74AC174 Technical data

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Data sheet acquired from Harris Semiconductor
SCHS241A

CD74AC174,

CD54/74ACT174

[ /Title
(CD74
AC174
,
CD74
ACT17
4
)

Sub-

ect
(HexD
Flip­Flop
with
Reset)

Autho
r ()

Key­words
(Har­ris
Semi­con­ductor,
Advan
ced
CMOS
,Harris
Semi­con­ductor,
Advan
ced
TTL)

Cre­ator ()

DOCI
NFO

September 1998 - Revised May 2000

Features

• Buffered Inputs

• Typical Propagation Delay

- 6.4ns at V

• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015

• SCR-Latchup-Resistant CMOS Process and Circuit
Design

• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption

• Balanced Propagation Delays

• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply

• ±24mA Output Drive Current

- Fanout to 15 FAST™ ICs

- Drives 50Ω Transmission Lines

= 5V, TA = 25oC, CL = 50pF

CC

Pinout

MR

Q0
D0
D1
Q1
D2
Q2

GND

Description

The CD74AC174 and ’ACT174arehex D flip-flops with reset
that utilize AdvancedCMOSLogictechnology. Information at
the D input is transferred to the Q output on the positive­going edge of the clock pulse. All six flip-flops are controlled
by a common clock (CP) and a common reset (
ting is accomplished by a low voltage level independent of
the clock.

Ordering Information

PART

NUMBER

CD74AC174E -55 to 125 16 Ld PDIP
CD74AC174M -55 to 125 16 Ld SOIC
CD54ACT174F3A -55 to 125 16 Ld CERDIP
CD74ACT174E -55 to 125 16 Ld PDIP
CD74ACT174M -55 to 125 16 Ld SOIC

NOTES:

1. When ordering, usethe entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Waf erand die forthis partnumber is availablewhichmeets allelec­trical specifications. Pleasecontact your local TI salesoffice or cus­tomer service for ordering information.

CD54ACT174

(CERDIP)

CD74AC174, CD74ACT174

(PDIP, SOIC)

TOP VIEW

16

1
2
3
4
5
6
7
8

V

CC

Q5

15
14

D5

13

D4

12

Q4
D3

11
10

Q3

9

CP

Hex D Flip-Flop with Reset

MR). Reset-

TEMP.

RANGE (oC) PACKAGE

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.

Copyright

© 2000, Texas Instruments Incorporated

1

Functional Diagram

9

CP

3

D0

CP
D
R

CD74AC174, CD54/74ACT174

2

Q0

D1

D2

D3

D4

D5
MR

4

6

11

13

14

1

5

Q1

7

Q2

10

Q3

12

Q4

15

Q5

GND = 8

= 16

V

CC

TRUTH TABLE (EACH FLIP-FLOP)

INPUTS OUTPUTS

RESET

(MR)

CLOCK

CP

DATA

Dn Qn

LXXL
H ↑ HH
H ↑ LL
HLXQ0

H = High Level (Steady State)
L = Low Level (Steady State)
X = Irrelevant
↑ = Transition from Low to High level
Q0 = Level before the Indicated Steady-State Input conditions
were established.

2

CD74AC174, CD54/74ACT174

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC VCC or Ground Current, I

CC orIGND

(Note 3) . . . . . . . . .±100mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC (Note 4)

AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V

ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Slew Rate, dt/dv

AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)

AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)

ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

3. For up to 4 outputs per device, add ±25mA for each additional output.

4. Unless otherwise specified, all voltages are referenced to ground.

5. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 5) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Maximum Junction Temperature (Plastic Package) . . . . . . . . . 1505oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

AC TYPES

High Level Input Voltage V

Low Level Input Voltage V

High Level Output Voltage V

IH

IL

OH

TEST

CONDITIONS

(V) IO(mA) MIN MAX MIN MAX MIN MAX

I

V

CC

(V)

25

o

C

-40oC TO
85oC

-55oC TO
125oC

- - 1.5 1.2 - 1.2 - 1.2 - V
3 2.1 - 2.1 - 2.1 - V

5.5 3.85 - 3.85 - 3.85 - V

- - 1.5 - 0.3 - 0.3 - 0.3 V
3 - 0.9 - 0.9 - 0.9 V

5.5 - 1.65 - 1.65 - 1.65 V

VIH or V

-0.05 1.5 1.4 - 1.4 - 1.4 - V

IL

-0.05 3 2.9 - 2.9 - 2.9 - V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

-4 3 2.58 - 2.48 - 2.4 - V

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

5.5 - - 3.85 - - - V

(Note 6, 7)

-50

5.5----3.85 - V

(Note 6, 7)

UNITSV

3

CD74AC174, CD54/74ACT174

DC Electrical Specifications (Continued)

PARAMETER SYMBOL

Low Level Output Voltage V

OL

TEST

CONDITIONS

(V) IO(mA) MIN MAX MIN MAX MIN MAX

I

VIH or V

0.05 1.5 - 0.1 - 0.1 - 0.1 V

IL

V

CC

(V)

25

o

C

0.05 3 - 0.1 - 0.1 - 0.1 V

0.05 4.5 - 0.1 - 0.1 - 0.1 V
12 3 - 0.36 - 0.44 - 0.5 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75

5.5 - - - 1.65 - - V

(Note 6, 7)

50

5.5-----1.65 V

(Note 6, 7)

Input Leakage Current I

I

VCC or

- 5.5 - ±0.1 - ±1-±1 µA

GND

Quiescent Supply Current
MSI

I

CC

VCC or

GND

0 5.5 - 8 - 80 - 160 µA

ACT TYPES

High Level Input Voltage V

IH

- - 4.5 to

2-2-2-V

5.5

Low Level Input Voltage V

IL

- - 4.5 to

- 0.8 - 0.8 - 0.8 V

5.5

High Level Output Voltage V

OH

VIH or V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

IL

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

5.5 - - 3.85 - - - V

(Note 6, 7)

-50

5.5----3.85 - V

(Note 6, 7)

Low Level Output Voltage V

OL

VIH or V

0.05 4.5 - 0.1 - 0.1 - 0.1 V

IL

24 4.5 - 0.36 - 0.44 - 0.5 V
75

5.5 - - - 1.65 - - V

(Note 6, 7)

50

5.5-----1.65 V

(Note 6, 7)

Input Leakage Current I

I

VCC or

- 5.5 - ±0.1 - ±1-±1 µA

GND

Quiescent Supply Current
MSI

AdditionalSupply Current per
Input Pin TTL Inputs High

I

CC

VCC or

GND

∆I

CC

V

CC

-2.1

0 5.5 - 8 - 80 - 160 µA

- 4.5 to

- 2.4 - 2.8 - 3 mA

5.5

1 Unit Load

NOTES:

6. Test one output at atime fora 1-second maximum duration. Measurement is madeby forcingcurrent and measuring voltage to minimize
power dissipation.

7. Test verifies a minimum 50Ω transmission-line-drive capability at 85

o

C, 75Ω at 125oC.

-40oC TO
85oC

-55oC TO
125oC

UNITSV

ACT Input Load Table

INPUT UNIT LOAD

Dn, MR 0.5

CP 0.83

NOTE: Unit load is ∆ICClimit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.

4

CD74AC174, CD54/74ACT174

Prerequisite For Switching Function

PARAMETER SYMBOL VCC (V)

AC TYPES

Data to CP Set-Up Time t

Hold Time t

Removal Time, MR to CP t

MR Pulse Width t

CP Pulse Width t

CP Frequency f

ACT TYPES

Data to CP Set-Up Time t

Hold Time t
Removal Time, MR to CP t
MR Pulse Width t
Clock Pulse Width t
CP Frequency f

SU

H

REM

W

W

MAX

SU

H

REM

W
W

MAX

-40oC TO 85oC -55oC TO 125oC

1.5 2 - 2 - ns

3.3

2-2-ns

(Note 9)

5

2-2-ns

(Note 10)

1.5 33 - 38 - ns

3.3 3.7 - 4.2 - ns
5 2.6 - 3 - ns

1.5 1.5 - 1.5 - ns

3.3 1.5 - 1.5 - ns
5 1.5 - 1.5 - ns

1.5 44 - 50 - ns

3.3 4.9 - 5.6 - ns
5 3.5 - 4 - ns

1.5 57 - 65 - ns

3.3 6.4 - 7.3 - ns
5 4.6 - 5.2 - ns

1.5 9 - 8 - MHz

3.3 77 - 68 - MHz
5 108 - 95 - MHz

5

2-2-ns

(Note 10)

5 2.2 - 2.5 - ns
5 1.5 - 1.5 - ns
5 3.5 - 4 - ns
5 5.4 - 6.2 - ns
5 91 - 80 - MHz

UNITSMIN MAX MIN MAX

Switching Specifications Input t

PARAMETER SYMBOL VCC (V)

AC TYPES

Propagation Delay, CP to Qn t

PLH

, tf = 3ns, CL= 50pF (Worst Case)

r

, t

PHL

1.5 - - 154 - - 169 ns

3.3

4.9 - 17.2 4.7 - 18.9 ns

(Note 9)

5

3.5 - 12.3 3.4 - 13.5 ns

(Note 10)

5

-40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX

CD74AC174, CD54/74ACT174

Switching Specifications Input t

, tf = 3ns, CL= 50pF (Worst Case) (Continued)

r

PARAMETER SYMBOL VCC (V)

Propagation Delay, MR to Qn t

PLH

, t

PHL

1.5 - - 165 - - 181 ns

3.3 5.2 - 18.5 5.1 - 20.3 ns
5 3.7 - 13.2 3.6 - 14.5 ns

Input Capacitance C
Power Dissipation Capacitance C

I

PD

- - -10- -10pF

- - 37 - - 37 - pF

(Note 11)

ACT TYPES

Propagation Delay, CP to Qn t

PLH

, t

PHL

5

3.6 - 12.6 3.5 - 14 ns

(Note 10)
Propagation Delay, MR to Qn t
Input Capacitance C
Power Dissipation Capacitance C

PLH

, t

PD

PHL

I

5 4 - 14.1 3.9 - 15.5 ns

- - -10- -10pF

- - 37 - - 37 - pF

(Note 11)

NOTES:

8. Limits tested 100%.

9. 3.3V Min is at 3.6V, Max is at 3V.

10. 5V Min is at 5.5V, Max is at 4.5V.

11. CPD is used to determine the dynamic power consumption per flip-flop.
PD=CPDV

2

fi+ Σ (CL+VCC2fo)+VCC∆ICCwhere fi= input frequency, fo= output frequency, CL= output load capacitance, VCC=

CC

supply voltage.

-40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX

INPUT LEVEL

GND

CP

V

S

t

PHL

V

t

S

W

V

S

t

V

PLH

S

FIGURE 1. PROPAGATION DELAYS

INPUT LEVEL

GND

INPUT

MR

V

S

CP

t

(Q)

Q

PHL

V

S

t

W

V

S

t

REM

V

S

FIGURE 2. RESET OR SET PREREQUISITE AND

PROPAGATION DELAYS

INPUT LEVEL

INPUT LEVEL

V

S

GND

GND

CP

D

V

S

tSU(L)

V

S

V

S

V

S

t

(L)

H

t

SU

(H)

V

S

tH(H)

V

S

FIGURE 3.

OUTPUT

R

(NOTE)

L

C

L

50pF

500Ω

DUT

OUTPUT

LOAD

NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.

AC ACT

Input Level V
Input Switching Voltage, V
Output Switching Voltage, V

S

S

0.5 V

0.5 V

CC

CC
CC

3V

1.5V

0.5 V

CC

FIGURE 4. PROPAGATION DELAY TIMES

6

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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright  2000, Texas Instruments Incorporated