CD74AC151,
[ /Title
(CD74
AC151
,
CD74
ACT15
1)
/Subject (8Input
Multiplexer)
/Autho
r ()
/Keywords
(Harris
Semiconductor,
Advan
ced
CMOS
)
/Creator ()
/DOCI
NFO
pdfmark
Data sheet acquired from Harris Semiconductor
SCHS236
September 1998
Features
• Buffered Inputs
• Typical Propagation Delay
- 6ns at V
• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015
• SCR-Latchup-Resistant CMOS Process and Circuit
Design
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
• Balanced Propagation Delays
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
- Drives 50Ω Transmission Lines
= 5V, TA = 25oC, CL = 50pF
CC
Pinout
GND
Description
The CD74AC151 and CD74ACT151 are 8-input digital multiplexers that utilize the Harris Advanced CMOS Logic technology. They have three binary control inputs (S0, S1, and
S2) and an active-LOW Enable (
inputs select 1 of 8channels. The output is both inverting (
and non-inverting (Y).
Ordering Information
PART
NUMBER
CD74AC151E 0 to 70oC, -40 to 85,
CD74ACT151E 0 to 70oC, -40 to 85,
CD74AC151M96 0 to 70oC, -40 to 85,
CD74ACT151M96 0 to 70oC, -40 to 85,
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris
customer service for ordering information.
CD74AC151, CD74ACT151
(PDIP, SOIC)
TOP VIEW
V
1
I
3
2
I
2
3
I
1
4
I
0
5
Y
6
Y
7
E
8
16
CC
15
I
4
14
I
5
13
I
6
12
I
7
11
S
0
10
S
1
9
S
2
CD74ACT151
8-Input Multiplexer
E) input. The three binary
Y)
TEMP.
RANGE (oC) PACKAGE
16 Ld PDIP E16.3
-55 to 125
16 Ld PDIP E16.3
-55 to 125
16 Ld SOIC M16.15
-55 to 125
16 Ld SOIC M16.15
-55 to 125
PKG.
NO.
[
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
Copyright
© Harris Corporation 1998
1
File Number 1980.1
CD74AC151, CD74ACT151
Functional Diagram
4
I
0
3
I
1
2
I
2
1
I
3
15
I
4
14
I
5
13
I
6
12
I
7
11
S
0
10
S
1
9
S
2
E
7
TRUTH TABLE
INPUTS OUTPUTS
ES2S
S
1
0
I
0
I
1
I
2
HXXXXXXXXXXXHL
LLLLLXXXXXXXHL
LLLLHXXXXXXXLH
LLLHXLXXXXXXHL
LLLHXHXXXXXXLH
LLHLXXLXXXXXHL
LLHLXXHXXXXXLH
LLHHXXXLXXXXHL
LLHHXXXHXXXXLH
LHLLXXXXLXXXHL
LHLLXXXXHXXXLH
LHLHXXXXXLXXHL
LHLHXXXXXHXXLH
LHHLXXXXXXLXHL
LHHLXXXXXXHXLH
LHHHXXXXXXXLHL
LHHHXXXXXXXHLH
H = HIGH voltage level, L = LOW voltage level, X = Don’t Care
5
Y
6
Y
GND = 8
V
= 16
CC
I
3
I
4
I
5
I
6
I
7
YY
2
CD74AC151, CD74ACT151
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Input Diode Current, I
IK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC Output Source or Sink Current per Output Pin, I
O
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA
DC VCC or Ground Current, I
CC orIGND
(Note 3) . . . . . . . . .±100mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC (Note 4)
AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V
ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V
Input Rise and Fall Slew Rate, dt/dv
AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)
AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)
ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. For up to 4 outputs per device, add ±25mA for each additional output.
4. Unless otherwise specified, all voltages are referenced to ground.
5. θJA is measured with the component mounted on an evaluation PC board in free air.
Thermal Resistance (Typical, Note 5) θJA (oC/W)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
CC
DC Electrical Specifications
PARAMETER SYMBOL
AC TYPES
High Level Input Voltage V
Low Level Input Voltage V
High Level Output Voltage V
IH
IL
OH
TEST
CONDITIONS
(V) IO(mA) MIN MAX MIN MAX MIN MAX
I
V
CC
(V)
25
o
C
-40oC TO
85oC
-55oC TO
125oC
- - 1.5 1.2 - 1.2 - 1.2 - V
3 2.1 - 2.1 - 2.1 - V
5.5 3.85 - 3.85 - 3.85 - V
- - 1.5 - 0.3 - 0.3 - 0.3 V
3 - 0.9 - 0.9 - 0.9 V
5.5 - 1.65 - 1.65 - 1.65 V
VIH or V
-0.05 1.5 1.4 - 1.4 - 1.4 - V
IL
-0.05 3 2.9 - 2.9 - 2.9 - V
-0.05 4.5 4.4 - 4.4 - 4.4 - V
-4 3 2.58 - 2.48 - 2.4 - V
-24 4.5 3.94 - 3.8 - 3.7 - V
-75
5.5 - - 3.85 - - - V
(Note 6, 7)
-50
5.5----3.85 - V
(Note 6, 7)
UNITSV
3
CD74AC151, CD74ACT151
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
Low Level Output Voltage V
OL
TEST
CONDITIONS
(V) IO(mA) MIN MAX MIN MAX MIN MAX
I
VIH or V
0.05 1.5 - 0.1 - 0.1 - 0.1 V
IL
V
CC
(V)
25
o
C
0.05 3 - 0.1 - 0.1 - 0.1 V
0.05 4.5 - 0.1 - 0.1 - 0.1 V
12 3 - 0.36 - 0.44 - 0.5 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75
5.5 - - - 1.65 - - V
(Note 6, 7)
50
5.5-----1.65 V
(Note 6, 7)
Input Leakage Current I
I
VCC or
- 5.5 - ±0.1 - ±1-±1 µA
GND
Quiescent Supply Current
MSI
I
CC
VCC or
GND
0 5.5 - 8 - 80 - 160 µA
ACT TYPES
High Level Input Voltage V
IH
- - 4.5 to
2-2-2-V
5.5
Low Level Input Voltage V
IL
- - 4.5 to
- 0.8 - 0.8 - 0.8 V
5.5
High Level Output Voltage V
OH
VIH or V
-0.05 4.5 4.4 - 4.4 - 4.4 - V
IL
-24 4.5 3.94 - 3.8 - 3.7 - V
-75
5.5 - - 3.85 - - - V
(Note 6, 7)
-50
5.5----3.85 - V
(Note 6, 7)
Low Level Output Voltage V
OL
VIH or V
0.05 4.5 - 0.1 - 0.1 - 0.1 V
IL
24 4.5 - 0.36 - 0.44 - 0.5 V
75
5.5 - - - 1.65 - - V
(Note 6, 7)
50
5.5-----1.65 V
(Note 6, 7)
Input Leakage Current I
I
VCC or
- 5.5 - ±0.1 - ±1-±1 µA
GND
Quiescent Supply Current
MSI
AdditionalSupply Current per
Input Pin TTL Inputs High
I
CC
VCC or
GND
∆I
CC
V
CC
-2.1
0 5.5 - 8 - 80 - 160 µA
- 4.5 to
- 2.4 - 2.8 - 3 mA
5.5
1 Unit Load
NOTES:
6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.
7. Test verifies a minimum 50Ω transmission-line-drive capability at 85
o
C, 75Ω at 125oC.
-40oC TO
85oC
-55oC TO
125oC
UNITSV
ACT Input Load Table
INPUT UNIT LOAD
I (All) 1
E1
S1
NOTE: Unit load is ∆ICClimit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.
4
CD74AC151, CD74ACT151
Switching Specifications Input t
, tf = 3ns, CL= 50pF (Worst Case)
r
PARAMETER SYMBOL VCC (V)
AC TYPES
Propagation Delay,
Any Data to Y
t
PLH
, t
PHL
1.5 - - 152 - - 169 ns
3.3
4.9 - 17.1 4.7 - 18.9 ns
(Note 9)
5
3.5 - 12.3 3.4 - 13.5 ns
(Note 10)
Propagation Delay,
Any Data to Y
t
PLH
, t
PHL
1.5 - - 169 - - 186 ns
3.3 5.4 - 19 5.2 - 20.9 ns
5 3.8 - 13.5 3.7 - 14.9 ns
Propagation Delay,
Any Select to Y
t
PLH
, t
PHL
1.5 - - 207 - - 228 ns
3.3 6.6 - 23.2 6.4 - 25.5 ns
5 4.7 - 16.5 4.6 - 18.2 ns
Propagation Delay,
Any Select to Y
t
PLH
, t
PHL
1.5 - - 223 - - 245 ns
3.3 7.1 - 24.9 6.9 - 27.4 ns
5 5.1 - 17.8 4.9 - 19.6 ns
Propagation Delay,
Any Enable to Y
t
PLH
, t
PHL
1.5 - - 139 - - 153 ns
3.3 4.4 - 15.5 4.3 - 17.1 ns
5 3.1 - 11.1 3.1 - 12.2 ns
Propagation Delay,
Any Enable to Y
t
PLH
, t
PHL
1.5 - - 153 - - 169 ns
3.3 4.9 - 17.2 4.7 - 18.9 ns
5 3.5 - 12.3 3.4 - 13.5 ns
Input Capacitance C
Power Dissipation Capacitance C
I
PD
- - -10- -10pF
- - 120 - - 120 - pF
(Note 11)
ACT TYPES
Propagation Delay,
Any Data to Y
Propagation Delay,
t
PLH
t
PLH
, t
PHL
5
4 - 14.1 3.9 - 15.5 ns
(Note 10)
, t
PHL
5 4.4 - 15.4 4.2 - 16.9 ns
Any Data to Y
Propagation Delay,
t
PLH
, t
PHL
5 5.2 - 18.4 5.1 - 20.2 ns
Any Select to Y
Propagation Delay,
t
PLH
, t
PHL
5 5.6 - 19.6 5.4 - 21.6 ns
Any Select to Y
Propagation Delay,
t
PLH
, t
PHL
5 3.1 - 11 3 - 12.1 ns
Any Enable to Y
Propagation Delay,
t
PLH
, t
PHL
5 3.5 - 12.3 3.4 - 13.5 ns
Any Enable to Y
Input Capacitance C
Power Dissipation Capacitance C
I
PD
- - -10- -10pF
- - 120 - - 120 - pF
(Note 11)
NOTES:
8. Limits tested at 100%.
9. 3.3V Min at 3.6V, Max at 3V.
10. 5V Min at 5.5V, Max at 4.5V.
11. CPD is used to determine the dynamic power consumption per device.
AC: PD = V
ACT: PD = V
2
fi(CPD + CL)
CC
2
fi(CPD + CL) + VCC∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
CC
-40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX
5
CD74AC151, CD74ACT151
IN OR S
t
r
90%
V
S
10%
t
PHL
Y
t
PLH
Y
t
V
S
t
PHL
V
S
t
f
INPUT LEVEL
GND
PLH
FIGURE 1. INPUTS OR SELECT TO OUTPUT PROPAGATION
DELAYS
OUTPUT
R
(NOTE)
L
C
L
50pF
500Ω
DUT
OUTPUT
LOAD
NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.
= 3ns tf = 3ns
t
ENABLE
SELECT
I
Y OUTPUT
Y OUTPUT
r
N
t
PHL
t
PLH
INPUT LEVEL
90%
V
S
10%
GND
V
S
t
PLH
t
PHL
V
S
FIGURE 2. ENABLE TO OUTPUT PROPAGATION DELAYS
CD74AC CD74ACT
Input Level V
Input Switching Voltage, V
Output Switching Voltage, V
S
S
0.5 V
0.5 V
FIGURE 3. PROPAGATION DELAY TIMES
CC
CC
CC
3V
1.5V
0.5 V
CC
6
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