55°C to 125°C
SOIC
M
AC112M
查询AC112M供应商查询AC112M供应商
CD54AC112, CD74AC112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS325 – JANUARY 2003
D
AC Types Feature 1.5-V to 5.5-V Operation
and Balanced Noise Immunity at 30% of the
Supply Voltage
D
Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
D
Balanced Propagation Delays
D
±24-mA Output Drive Current
– Fanout to 15 F Devices
D
SCR-Latchup-Resistant CMOS Process and
Circuit Design
D
Exceeds 2-kV ESD Protection Per
CD54AC112 ...F PACKAGE
CD74AC112 ...E OR M PACKAGE
1CLK
1PRE
1K
1J
1Q
1Q
2Q
GND
(TOP VIEW)
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
V
CC
1CLR
2CLR
2CLK
2K
2J
2PRE
2Q
MIL-STD-883, Method 3015
description/ordering information
The ’AC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset
(PRE
) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE
and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to
the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and
is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs
may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle
flip-flops by tying J and K high.
ORDERING INFORMA TION
T
A
PDIP – E Tube CD74AC112E CD74AC112E
–
CDIP – F Tube CD54AC112F3A CD54AC112F3A
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
PACKAGE
–
†
Tube CD74AC112M
Tape and reel CD74AC112M96
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
CD54AC112, CD74AC112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS325 – JANUARY 2003
FUNCTION TABLE
(each flip-flop)
INPUTS
PRE CLR CLK J K Q Q
L H X X X H L
H LXXXLH
L LXXXH†H
H H ↓ LLQ0Q
H H ↓ HLHL
H H ↓ LHLH
H H ↓ H H Toggle
H H H X X Q
†
Output states are unpredictable if PRE
simultaneously after both being low at the same time.
logic diagram (positive logic)
OUTPUTS
†
0
Q
0
0
and CLR go high
Q Q
PRE
K
CLK
CLR
J
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
(VI < 0 V or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0 V or VO > VCC) (see Note 1) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
(VO > 0 V or VO < VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 2): E package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
M package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
∆t/∆v
Input transition rise or fall rate
ns/V
CC
CD54AC112, CD74AC112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS325 – JANUARY 2003
recommended operating conditions (see Note 3)
TA = 25°C
MIN MAX MIN MAX MIN MAX
V
V
V
V
V
I
OH
I
OL
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 1.5 5.5 1.5 5.5 1.5 5.5 V
CC
VCC = 1.5 V 1.2 1.2 1.2
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
High-level output current VCC = 4.5 V to 5.5 V –24 –24 –24 mA
Low-level output current VCC = 4.5 V to 5.5 V 24 24 24 mA
p
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
VCC = 3 V
VCC = 5.5 V 3.85 3.85 3.85
VCC = 1.5 V 0.3 0.3 0.3
VCC = 3 V
VCC = 5.5 V 1.65 1.65 1.65
VCC = 1.5 V to 3 V 50 50 50
VCC = 3.6 V to 5.5 V 20 20 20
2.1 2.1 2.1
–55°C to
125°C
0.9 0.9 0.9
CC
CC
0 V
0 V
CC
CC
–40°C to
85°C
0 V
0 V
CC
CC
UNIT
V
V
V
V
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS V
1.5 V 1.4 1.4 1.4
IOH = –50 µA
V
OH
V
OL
I
I
I
CC
C
†
i
T est one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize
power dissipation. T est verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.
VI = VIH or V
VI = VIH or V
VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
VI = VCC or GND, IO = 0 5.5 V 4 80 40 µA
IL
IL
IOH = –4 mA 3 V 2.58 2.4 2.48
IOH = –24 mA 4.5 V 3.94 3.7 3.8
IOH = –50 mA
IOH = –75 mA
IOL = 50 µA
IOL = 12 mA 3 V 0.36 0.5 0.44
IOL = 24 mA 4.5 V 0.36 0.5 0.44
IOL = 50 mA
IOL = 75 mA
†
†
†
†
3 V 2.9 2.9 2.9
4.5 V 4.4 4.4 4.4
5.5 V 3.85
5.5 V 3.85
1.5 V 0.1 0.1 0.1
3 V 0.1 0.1 0.1
4.5 V 0.1 0.1 0.1
5.5 V 1.65
5.5 V 1.65
TA = 25°C
MIN MAX MIN MAX MIN MAX
–55°C to
125°C
10 10 10 pF
–40°C to
85°C
UNIT
V
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
CD54AC112, CD74AC112
twPulse duration
ns
twPulse duration
ns
twPulse duration
ns
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS325 – JANUARY 2003
timing requirements over recommended operating free-air temperature range, V
otherwise noted)
–55°C to
125°C
MIN MAX MIN MAX
f
clock
t
su
t
h
t
rec
Clock frequency 8 9 MHz
CLK high or low 63 55
CLR or PRE low 56 49
Setup time, before CLK↓ J or K 50 44 ns
Hold time, after CLK↓ J or K 0 0 ns
Recovery time, before CLK↓ CLR↑ or PRE↑ 31 27 ns
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted)
–55°C to
125°C
MIN MAX MIN MAX
f
clock
t
su
t
h
t
rec
Clock frequency 71 81 MHz
CLK high or low 7 6
CLR or PRE low 6.3 5.5
Setup time, before CLK↓ J or K 5.6 4.9 ns
Hold time, after CLK↓ J or K 0 0 ns
Recovery time, before CLK↓ CLR↑ or PRE↑ 3.5 3..1 ns
= 1.5 V (unless
CC
–40°C to
85°C
= 3.3 V ± 0.3 V
CC
–40°C to
85°C
UNIT
UNIT
timing requirements over recommended operating free-air temperature0 range, V
(unless otherwise noted)
–55°C to
125°C
MIN MAX MIN MAX
f
clock
t
su
t
h
t
rec
Clock frequency 100 114 MHz
CLK high or low 5 4.4
CLR or PRE low 4.5 3.9
Setup time, before CLK↓ J or K 4 3.5 ns
Hold time, after CLK↓ J or K 0 0 ns
Recovery time, before CLK↓ CLR↑ or PRE↑ 2.5 2.2 ns
= 5 V ± 0.5 V
CC
–40°C to
85°C
UNIT
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
(INPUT)
(OUTPUT)
t
Q
Q
ns
t
Q
Q
ns
(INPUT)
(OUTPUT)
t
Q
Q
ns
t
Q
Q
ns
(INPUT)
(OUTPUT)
t
Q
Q
ns
t
Q
Q
ns
CD54AC112, CD74AC112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS325 – JANUARY 2003
switching characteristics over recommended operating free-air temperature range,
V
= 1.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
CC
–55°C to
125°C
MIN MAX MIN MAX
8 9 MHz
129 117
153 139
129 117
153 139
PARAMETER
f
max
PLH
PHL
FROM
CLK
CLR or PRE
CLK
CLR or PRE
TO
or
or
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
CC
–55°C to
125°C
MIN MAX MIN MAX
71 81 MHz
3.6 14.4 3.7 13.1
4.3 17.1 4.4 15.5
3.6 14.4 3.7 13.1
4.3 17.1 4.4 15.5
PARAMETER
f
max
PLH
PHL
FROM
CLK
CLR or PRE
CLK
CLR or PRE
TO
or
or
–40°C to
85°C
–40°C to
85°C
UNIT
UNIT
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
CC
PARAMETER
f
max
PLH
PHL
FROM
CLK
CLR or PRE
CLK
CLR or PRE
TO
or
or
–55°C to
125°C
MIN MAX MIN MAX
100 114 MHz
2.6 10.3 2.7 9.4
3.1 12.2 3.2 11.1
2.6 10.3 2.7 9.4
3.1 12.2 3.2 11.1
–40°C to
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TYP UNIT
C
pd
Power dissipation capacitance 56 pF
85°C
UNIT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
CD54AC112, CD74AC112
DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCHS325 – JANUARY 2003
PARAMETER MEASUREMENT INFORMATION
S1
50% V
t
r
CC
t
f
†
†
CC
t
50% V
50% V
t
PHL
t
PLH
.
dis
rec
CC
CC
50%
From Output
Under Test
CL = 50 pF
(see Note A)
†
When VCC = 1.5 V, R1 = R2 = 1 kΩ
CLR
Input
CLK
VOLTAGE WAVEFORMS
Input
In-Phase
Output
Out-of-Phase
Output
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. For clock inputs, f
E. The outputs are measured one at a time with one input transition per measurement.
F. t
G. t
H. t
I. All parameters and waveforms are not applicable to all devices.
50% V
CC
t
PLH
50%
t
PHL
VOLTAGE WAVEFORMS
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
Phase relationships between waveforms are arbitrary.
and t
PLH
PZL
PLZ
and t
and t
PHL
PZH
PHZ
R1 = 500 Ω
R2 = 500 Ω
LOAD CIRCUIT
RECOVERY TIME
90% 90%
50% V
10% 10%
is measured with the input duty cycle at 50%.
max
are the same as tpd.
are the same as ten.
are the same as t
2 × V
Open
GND
50% V
10%10%
90%90%
V
0 V
V
0 V
CC
CC
CC
TEST S1
t
w
50% V
50% V
50% V
Open
2 × V
GND
CC
50% V
CC
t
h
CC
CC
CC
50% V
50% V
20% V
80% V
CC
50% V
10%10%
t
CC
t
PLZ
t
PHZ
V
0 V
f
CC
CC
CC
V
0 V
V
CC
0 V
V
CC
0 V
≈V
V
OL
V
OH
≈0 V
CC
CC
CC
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Input
Reference
Input
Data
Input
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
V
CC
0 V
V
OH
CC
V
OL
t
f
V
OH
V
OL
t
r
Waveform 1
S1 at 2 × V
(see Note B)
Waveform 2
(see Note B)
50%
Output
Control
Output
Output
S1 at GND
OUTPUT ENABLE AND DISABLE TIMES
50% V
CC
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
90% 90%
t
r
VOLTAGE WAVEFORMS
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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