TEXAS INSTRUMENTS CD74HC85, CD54HCT85, CD74HCT85 Technical data

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Data sheet acquired from Harris Semiconductor

[ ( H C H ) / j ( S C L 4 M t C p

SCHS136E

CD54HC85, CD74HC85,

CD54HCT85, CD74HCT85

High-Speed CMOS Logic

/Title CD74

C85, D74 CT85

Subect High

peed

MOS

ogic

-Bit agni-

ude

om-

ara-

August 1997 - Revised October 2003

Features

• Buffered Inputs and Outputs

• Typical Propagation Delay: 13ns (Data to Output at V

= 5V, CL = 15pF, TA = 25oC

• Serial or Parallel Expansion Without External Gating

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL Logic ICs

• HC Types

- 2V to 6V Operation

- High NoiseImmunity: N

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, I

= 30%, NIH= 30%of VCCat

≤ 1µA at VOL, V

C to 125oC

Pinout

CD54HC85, CD54HCT85 (CERDIP)

CD74HC85 (PDIP, SOIC, SOP, TSSOP)

CD74HCT85 (PDIP, SOIC)

TOP VIEW

B3 (A < B) IN (A = B) IN (A > B) IN

(A > B) OUT (A = B) OUT (A < B) OUT

GND

1 2 3 4 5 6 7 8

A1 B1

11 10

4-Bit Magnitude Comparator

Description

The ’HC85 and ’HCT85 are high speed magnitude comparators that use silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits.

These 4-bit devices compare two binary, BCD, or other monotonic codes and present the three possible magnitude results at the outputs (A > B, A < B, and A = B). The 4-bit input words are weighted (A0 to A3 and B0 to B3), where A3 and B

are the most signiﬁcant bits.

The devices are expandable without external gating, in both serial and parallel fashion. The upper part of the truth table indicates operation using a single device or devices in a serially expanded application. The parallel expansion scheme is described by the last three entries in the truth table.

Ordering Information

TEMP. RANGE

PART NUMBER

CD54HC85F3A -55 to 125 16 Ld CERDIP CD54HCT85F3A -55 to 125 16 Ld CERDIP CD74HC85E -55 to 125 16 Ld PDIP CD74HC85M -55 to 125 16 Ld SOIC CD74HC85MT -55 to 125 16 Ld SOIC CD74HC85M96 -55 to 125 16 Ld SOIC CD74HC85NSR -55 to 125 16 Ld SOP CD74HC85PW -55 to 125 16 Ld TSSOP CD74HC85PWR -55 to 125 16 Ld TSSOP CD74HC85PWT -55 to 125 16 Ld TSSOP CD74HCT85E -55 to 125 16 Ld PDIP CD74HCT85M -55 to 125 16 Ld SOIC CD74HCT85MT -55 to 125 16 Ld SOIC CD74HCT85M96 -55 to 125 16 Ld SOIC

(oC) PACKAGE

NOTE: When ordering, use the entire part number. The sufﬁxes 96 and R denote tape and reel. The sufﬁx T denotes a small-quantity reel of 250.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright

CD54HC85, CD74HC85, CD54HCT85, CD74HCT85

PFunctional Diagram

(A < B) OUT

(A = B) OUT

(A > B) OUT

B3 B2 B1 B0

2 3 4

1 14 11

(A < B) IN (A = B) IN (A > B) IN

TRUTH TABLE

COMPARING INPUTS CASCADING INPUTS OUTPUTS

A3, B3 A2, B2 A1, B1 A0, B0 A > B A < B A = B A > B A < B A = B

SINGLE DEVICE OR SERIES CASCADING

A3 > B3 X X X X X X H L L A3 < B3 X X X X X X L H L A3 = B3 A2 >B2 X X X X X H L L A3 = B3 A2 < B2 X X X X X L H L A3 = B3 A2 = B2 A1 > B1 X X X X H L L A3 = B3 A2 = B2 A1 < B1 X X X X L H L A3 = B3 A2 = B2 A1 = B1 A0 > B0 X X X H L L A3 = B3 A2 = B2 A1 = B1 A0 < B0 X X X L H L A3 = B3 A2 = B2 A1 = B1 A0 = B0 H L L H L L A3 = B3 A2 = B2 A1 = B1 A0 = B0 L H L L H L A3 = B3 A2 = B2 A1 = B1 A0 = B0 L L H L L H

PARALLEL CASCADING

A3 = B3 A2 = B2 A1 = B1 A0 = B0 X X H L L H A3 = B3A2 = B2A1 = B1A0 = B0HHLLLL A3 = B3 A2 = B2S A1 = B1 A0 = B0 L L L H H L

H = High Voltage Level, L = Low Voltage, Level, X = Don’t Care

CD54HC85, CD74HC85, CD54HCT85, CD74HCT85

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

Package Thermal Impedance, θJA(see Note 1):

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67oC/W

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73oC/W

NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W

PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

DC Electrical Speciﬁcations

PARAMETER SYMBOL

HC TYPES

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage CMOS Loads

High Level Output Voltage TTL Loads

Low Level Output Voltage CMOS Loads

Low Level Output Voltage TTL Loads

Input Leakage Current

Quiescent Device Current

TEST

CONDITIONS

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

VCC or

0 6 - - 8 - 80 - 160 µA

GND

CD54HC85, CD74HC85, CD54HCT85, CD74HCT85

DC Electrical Speciﬁcations (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

HCT TYPES

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage CMOS Loads

High Level Output Voltage TTL Loads

Low Level Output Voltage CMOS Loads

Low Level Output Voltage TTL Loads

Input Leakage Current

Quiescent Device Current

Additional Quiescent Device Current Per Input Pin: 1 Unit Load

NOTE:

2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

∆I

(Note 2)

- - 4.5 to

VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V

4 4.5 - - 0.26 - 0.33 - 0.4 V

VCCand

GND

VCC or

GND

-2.1

0 5.5 - ±0.1 - ±1-±1 µA

0 5.5 - - 8 - 80 - 160 µA

- 4.5 to

(V)

5.5

25oC -40oC TO 85oC -55oC TO 125oC

2--2- 2 - V

- - 0.8 - 0.8 - 0.8 V

- 100 360 - 450 - 490 µA

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

A0-A3, B0-B3 and (A = B) IN 1.5

(A > B) IN, (A < B) IN 1

NOTE: Unit Load is ∆I 360µA max at 25oC.

Switching Speciﬁcations Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay, An, Bn to (A > B) OUT, (A < B) OUT

An, Bn to (A = B) OUT t

limit speciﬁed in DC Electrical Table, e.g.

, tf = 6ns

PLH,tPHLCL

-40oC TO

TEST

CONDITIONS VCC(V)

= 50pF 2 - - 195 - 245 - 295 ns

4.5 - - 39 - 47 - 59 ns CL= 15pF 5 - 16 - - - - - ns CL= 50pF 6 - - 33 - 42 - 50 ns

= 50pF 2 - - 175 - 240 - 265 ns

4.5 - - 35 - 44 - 53 ns CL= 15pF 5 - 14 - - - - - ns CL= 50pF 6 - - 30 - 37 - 45 ns

25oC

85oC

-55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

CD54HC85, CD74HC85, CD54HCT85, CD74HCT85

Switching Speciﬁcations Input t

, tf = 6ns (Continued)

TEST

PARAMETER SYMBOL

(A > B) IN, (A < B) IN, (A = B) IN to (A > B) OUT, (A < B) OUT

PLH,tPHLCL

CONDITIONS VCC(V)

= 50pF 2 - - 140 - 175 - 210 ns

4.5 - - 28 - 35 - 42 ns CL= 15pF 5 - 11 - - - - - ns CL= 50pF 6 - - 24 - 30 - 36 ns

(A > B) IN to (A = B) OUT t

PLH,tPHLCL

= 50pF 2 - - 120 - 150 - 180 ns

4.5 - - 24 - 30 - 36 ns CL= 15pF 5 - 9 - - - - - ns CL= 50pF 6 - - 20 - 26 - 31 ns

Power Dissipation Capacitance

-5-24-----pF

(Notes 3, 4) Output Transition Times

(Figure 1)

TLH

, t

THLCL

= 50pF 2 - - 75 - 95 - 110 ns

4.5 - - 15 - 19 - 22 ns

6 - - 13 - 16 - 19 ns

Input Capacitance C

- - - - 10 - 10 - 10 pF

HCT TYPES

Propagation Delay, An, Bn to (A > B) OUT, (A < B) OUT

An, Bn to (A = B) OUT t

PLH,tPHLCL

= 50pF 4.5 - - 37 - 46 - 56 ns

CL= 15pF 5 - 15 - - - - - ns

= 50pF 4.5 - - 40 - 50 - 60 ns

CL= 15pF 5 - 17 - - - - - ns

(A > B) IN, (A < B) IN, (A = B) IN to (A > B) OUT, (A < B) OUT

(A > B) IN to (A = B) OUT t

PLH,tPHLCL

= 50pF 4.5 - - 30 - 38 - 45 ns

CL= 15pF 5 - 12 - - - - - ns

= 50pF 4.5 - - 31 - 39 - 47 ns

CL= 15pF 5 - 13 - - - - - ns

Output Transition Times

TLH

, t

THLCL

= 50pF 4.5 - - 15 - 19 - 22 ns

(Figure 1) Power Dissipation Capacitance

-5-26-----pF

(Notes 3, 4) Input Capacitance C

- - - - 10 - 10 - 10 pF

NOTES:

3. CPD is used to determine the dynamic power consumption, per gate/package.

4. PD = V

fi(CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

25oC

-40oC TO 85oC

-55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

Test Circuits and Waveforms

tr = 6ns tf = 6ns

GND

TLH

PHL

90% 50% 10%

90%

50%

10%

PLH

INPUT

INVERTING

OUTPUT

THL

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

= 6ns

PLH

1.3V

10%

90%

TLH

tr = 6ns

INPUT

INVERTING

OUTPUT

THL

PHL

2.7V

1.3V

0.3V

FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

GND

CD54HC85, CD74HC85, CD54HCT85, CD74HCT85

Test Circuits and Waveforms

LEAST SIGNIFICANT

4-BITS OF EACH WORD

MOST SIGNIFICANT

4-BITS OF EACH WORD

FIGURE 3. SERIES CASCADING - COMPARING 12-BIT WORDS

GND

A0 A1 A2 A3 B0 B1 B2 B3

A4 A5 A6 A7 B4 B5 B6 B7

A0 A1 A2 A3 B0 B1 B2 B3

(A > B) IN (A = B) IN (A < B) IN

A0 A1

CD74HC85

CD74HCT85

A3 B0 B1 B2 B3

(A > B) IN (A = B) IN (A < B) IN

A4 A5

CD74HC85

CD74HCT85

A7 B4

(A > B) OUT

(A = B) OUT

(A < B) OUT

(A > B) IN (A = B) IN (A < B) IN

A0 A1

CD74HC85

CD74HCT85 A3 B0

(A > B) OUT

(A = B) OUT

(A < B) OUT

OUTPUTS

CD54HC85, CD74HC85, CD54HCT85, CD74HCT85

Test Circuits and Waveforms

GND

B1 A1 B0 A0

VCC GND

CD74HC85

CD74HCT85

A3 B2 A2

(A < B) OUT

(A = B) OUT

(A > B) OUT

B0 A0 (A < B) IN (A = B) IN (A > B) IN

CD74HC85

CD74HCT85

A3 B2 A2

(A < B) OUT

(A = B) OUT

(A > B) OUT

B0 A0 (A < B) IN (A = B) IN (A > B) IN

OUTPUTS

B6 A6 B5 A5 B4 A4 B3 A3 B2

GND

CD74HC85

CD74HCT85

(A < B) OUT

(A = B) OUT

B1 A1

(A > B) OUT B0 A0

(A < B) IN (A = B) IN (A > B) IN

B11 A11 B10 A10

B9 A9 B8 A8 B7

GND

FIGURE 4. PARALLEL CASCADING - COMPARING 12-BIT WORDS

CD74HC85

CD74HCT85

A3 B2 A2

(A > B) OUT

(A = B) OUT

(A < B) OUT

B0 A0 (A < B) IN (A = B) IN (A > B) IN

OUTPUT

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

5962-8867201EA ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC

8601301EA ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC

CD54HC85F3A ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC

CD54HCT85F3A ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC

CD74HC85E ACTIVE PDIP N 16 25 Pb-Free

CD74HC85EE4 ACTIVE PDIP N 16 25 Pb-Free

CD74HC85M ACTIVE SOIC D 16 40 Green (RoHS &

CD74HC85M96 ACTIVE SOIC D 16 2500 Green (RoHS &

CD74HC85M96E4 ACTIVE SOIC D 16 2500 Green (RoHS &

CD74HC85ME4 ACTIVE SOIC D 16 40 Green (RoHS &

CD74HC85MT ACTIVE SOIC D 16 250 Green (RoHS &

CD74HC85MTE4 ACTIVE SOIC D 16 250 Green (RoHS &

CD74HC85NSR ACTIVE SO NS 16 2000 Green (RoHS &

CD74HC85NSRE4 ACTIVE SO NS 16 2000 Green (RoHS &

CD74HC85PW ACTIVE TSSOP PW 16 90 Green (RoHS &

CD74HC85PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS &

CD74HC85PWR ACTIVE TSSOP PW 16 2000 Green (RoHS &

CD74HC85PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS &

CD74HC85PWT ACTIVE TSSOP PW 16 250 Green (RoHS &

CD74HC85PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS &

CD74HCT85E ACTIVE PDIP N 16 25 Pb-Free

CD74HCT85EE4 ACTIVE PDIP N 16 25 Pb-Free

CD74HCT85M ACTIVE SOIC D 16 40 Green (RoHS &

CD74HCT85M96 ACTIVE SOIC D 16 2500 Green (RoHS &

CD74HCT85M96E4 ACTIVE SOIC D 16 2500 Green (RoHS &

CD74HCT85ME4 ACTIVE SOIC D 16 40 Green (RoHS &

CD74HCT85MT ACTIVE SOIC D 16 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

no Sb/Br)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-NC-NC-NC

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-NC-NC-NC

CU NIPDAU Level-1-260C-UNLIM

17-Oct-2005

(3)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

17-Oct-2005

(3)

no Sb/Br)

CD74HCT85MTE4 ACTIVE SOIC D 16 250 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

1,20 MAX

0,30 0,19

4,50 4,30

PINS **

Seating Plane

0,15 0,05

DIM

0,10

6,60 6,20

0,10

0,15 NOM

0°–8°

2016

Gage Plane

0,25

0,75 0,50

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

4040064/F 01/97

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TEXAS INSTRUMENTS CD74HC85, CD54HCT85, CD74HCT85 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual