Texas Instruments CD74HCT688M96, CD74HCT688M, CD74HCT688E, CD74HC688PWR, CD74HC688M96 Datasheet

CD74HC688,

/
j

[ /Title
(CD74
HC688
,
CD74
HCT68

8)
Sub­ect

(High
Speed
CMOS

Data sheet acquired from Harris Semiconductor
SCHS196

September 1997

Features

• Cascadable

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High NoiseImmunity: N

V

= 5V

CC

= 30%, NIH= 30%of VCCat

IL

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

≤ 1µA at VOL, V

l

o

C to 125oC

OH

CD74HCT688

High Speed CMOS Logic

8-Bit Magnitude Comparator

Description

The Harris CD74HC688 and CD74HCT688 are 8-bit
magnitude comparators designed for use in computer and
logic applications that require the comparison of two 8-bit
binary words. When the compared words are equal the
output (Y) is low and can be used as the enabling input for
the next device in a cascaded application.

Ordering Information

PKG.

PART NUMBER TEMP. RANGE (oC) PACKAGE

CD74HC688E -55 to 125 20 Ld PDIP E20.3
CD74HCT688E -55 to 125 20 Ld PDIP E20.3
CD74HC688M -55 to 125 20 Ld SOIC M20.3
CD74HCT688M -55 to 125 20 Ld SOIC M20.3
CD54HC688 -55 to 125 Wafer

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Die for this part number is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.

NO.

Pinout

CD74HC688, CD74HCT688

(PDIP, SOIC)

TOP VIEW

1

E

A0

2

B0

3

A1

4

B1

5

A2

6

B2

7
8

A3

9

B3

GND

10

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

1

V

20

CC

Y

19

B7

18

A7

17

B6

16

A6

15

B5

14

A5

13
12

B4
A4

11

File Number 1646.1

Functional Diagram

CD74HC688, CD74HCT688

2

A0

4

A1

6

A2

8

A3

11

A4

13

A5

15

A6

17

A7
B0
B1
B2
B3
B4
B5
B6
B7

3
5
7

9
12
14
16
18

Y

19

E

1

TRUTH TABLE

INPUTS OUPUTS

A, B EY

A = B L L
A ≠ BL H

XH H

NOTES: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

2

Logic Diagram

A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7

2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18

CD74HC688, CD74HCT688

E

1

10

20

GND

V

CC

19

Y

3