Texas Instruments CD74HCT541M96, CD74HCT541M, CD74HCT541E, CD74HCT540M96, CD74HCT540M Datasheet

CD74HC540, CD74HCT540,

[ /Title
(CD74
HC540
,
CD74
HCT54
0,
CD74
HC541
,
CD74
HCT54

Data sheet acquired from Harris Semiconductor
SCHS189

January 1998

Features

• CD74HC540, CD74HCT540 . . . . . . . . . . . . . . . Inverting

• CD74HC541, CD74HCT541 . . . . . . . . . . . . . .Non-Inverting

• Buffered Inputs

• Three-State Outputs

• Bus Line Driving Capability

• Typical Propagation Delay = 9ns at V
C

= 15pF, TA = 25oC

L

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, NIH = 30% of V

IL

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

≤ 1µA at VOL, V

l

CC

= 5V,

o

C to 125oC

CD74HC541, CD74HCT541

High Speed CMOS Logic

Octal Buffer and Line Drivers, Three-State

Description

The Harris CD74HC540 and CD74HCT540 are Inverting
Octal Buffers and Line Drivers with Three-State Outputs and
the capability to drive 15 LSTTL loads. The Harris
CD74HC541 and CD74HCT541 are Non-Inverting Octal Buff­ers and Line Drivers with Three-State Outputs that can drive

OH

15 LSTTL loads. The Output Enables (
trol the Three-State Outputs. If either
outputs will be in the high impedance state. For data output
OE1 and OE2 both must be LOW.

Ordering Information

TEMP.

CC

PART NUMBER

CD74HC540E -55 to 125 20 Ld PDIP E20.3
CD74HCT540E -55 to 125 20 Ld PDIP E20.3
CD74HC541E -55 to 125 20 Ld PDIP E20.3
CD74HCT541E -55 to 125 20 Ld PDIP E20.3
CD74HC540M -55 to 125 20 Ld SOIC M20.3
CD74HCT540M -55 to 125 20 Ld SOIC M20.3
CD74HC541M -55 to 125 20 Ld SOIC M20.3
CD74HCT541M -55 to 125 20 Ld SOIC M20.3

NOTES:

1. When ordering, use the entire partnumber. Add thesuffix 96 to
obtain the variant in the tape and reel.

2. Wafer and die forthis part number is availablewhich meets all
electrical specifications.Please contact yourlocal sales office or
Harris customer service for ordering information.

RANGE (oC) PACKAGE

OE1) and (OE2) con-

OE1 or OE2 is HIGH the

PKG.

NO.

Pinouts

CD74HC540, CD74HCT540

(PDIP, SOIC)

TOP VIEW

1

OE

A0

2

A1

3

A2

4

A3

5

A4

6

A5

7
8

A6

9

A7

GND

10

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

V

20

CC

OE2

19

Y0

18

Y1

17

Y2

16

Y3

15

Y4

14

Y5

13
12

Y6

11

Y7 11

1

CD74HC541, CD74HCT541

1

OE1

A0

2

A1

3

A2

4

A3

5

A4

6

A5

7
8

A6

9

A7

GND

10

(PDIP, SOIC)

TOP VIEW

V

20

CC

OE2

19

Y0

18

Y1

17

Y2

16

Y3

15

Y4

14

Y5

13
12

Y6
Y7

File Number 1659.2

CD74HC540, CD74HCT540, CD74HC541, CD74HCT541CD74HC540, CD74HCT540, CD74HC541, CD74HCT541

Functional Diagram

OE

A

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

OE

B

540 541

Y

Y

0

Y

Y

1

Y

Y

2

Y

Y

3

Y

Y

4

Y

Y

5

Y

Y

6

Y

Y

7

0

1

2

3

4

5

6

7

TRUTH TABLE

INPUTS OUTPUTS

OE1 OE2 An 540 541

LLHLH
HXXZZ
XHXZZ

LLLHL

NOTE:
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance

2

CD74HC540, CD74HCT540, CD74HC541, CD74HCT541CD74HC540, CD74HCT540, CD74HC541, CD74HCT541

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

V

IH

V

IL

V

OH

V

OL

I

I

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

CC

(V)

o

C -40oC TO 85oC -55oCTO125oC

25

UNITSV

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - - V

-6 4.5 3.98 - - 3.84 - 3.7 - V

-7.8 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - - V
6 4.5 - - 0.26 - 0.33 - 0.4 V

7.8 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1µA

GND

3

CD74HC540, CD74HCT540, CD74HC541, CD74HCT541CD74HC540, CD74HCT540, CD74HC541, CD74HCT541

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Quiescent Device

I

CC

Current
Three-State Leakage

Current

I

OZ

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

V

IL

V

OH

CMOS Loads
High Level Output

Voltage
TTL Loads

Low Level Output
Voltage

V

OL

CMOS Loads
Low Level Output

Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Three-State Leakage
Current

Additional Quiescent
Device Current Per

I

I

I

CC

I

OZ

∆I

CC

Input Pin: 1 Unit Load

NOTE: For dual-supply systems theoretical worst case (V

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

VCC or

0 6 - - 8 - 80 - 160 µA

GND

VILor VIHVO =

VCC or

GND

- - 4.5 to

- - 4.5 to

VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-6 4.5 3.98 - - 3.84 - 3.7 - V

VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V

6 4.5 - - 0.26 - 0.33 - 0.4 V

VCCand

0 5.5 - ±0.1 - ±1-±1µA

GND

VCC or

0 5.5 - - 8 - 80 - 160 µA

GND

VILor VIHVO =

VCC or

GND

V

CC

- 4.5 to

-2.1

o

C -40oC TO 85oC -55oCTO125oC

V

CC

25

(V)

6--±0.5 - ±5.0 - ±10 µA

2--2 - 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

5.5 - - ±0.5 - ±5.0 - ±10 µA

- 100 360 - 450 - 490 µA

5.5

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

UNITSV

HCT Input Loading Table

UNIT LOADS

INPUT

A0 - A7 1 0.4

OE2 0.75 0.75
OE1 1.15 1.15

NOTE: Unit loadis ∆ICClimit specificin DC ElectricalSpecifications
Table, e.g., 360µA max. at 25oC.

HCT540 HCT541

4

CD74HC540, CD74HCT540, CD74HC541, CD74HCT541CD74HC540, CD74HCT540, CD74HC541, CD74HCT541

Switching Specifications C

PARAMETER SYMBOL

= 50pF, Input tr, tf= 6ns

L

TEST

CONDITIONS V

CC

(V)

25

o

C

-40oC TO
85oC

-55oC TO
125oC

HC TYPES

Propagation Delay t

PLH

, t

PHLCL

= 50pF

Data to Outputs (540) 2 - - 110 - 140 - 165 ns

4.5 - - 22 - 28 - 33 ns

C

= 15pF 5 - 9 - - - - - ns

L

C

= 50pF 6 - - 19 - 24 - 28 ns

L

Data to Outputs (541) t

PLZ,tPHZ

CL = 50pF 2 - - 115 - 145 - 175 ns

4.5 - - 23 - 29 - 35 ns

C

= 15pF 5 - 9 - - - - - ns

L

C

= 50pF 6 - - 20 - 25 - 30 ns

L

Output Enable and Disable
to Outputs (540)

t

PLZ,tPHZ

CL = 50pF 2 - - 160 - 200 - 240 ns

4.5 - - 32 - 40 - 48 ns
CL = 15pF 5 - 13 - - - - - ns
C

= 50pF 6 - - 27 - 34 - 41 ns

L

Output Enable and Disable
to Outputs (541)

Output Transition Time t

t

PLZ,tPHZ

, t

THL

TLHCL

CL = 50pF 2 - - 160 - 200 - 240 ns

4.5 - - 32 - 40 - 48 ns
C

= 15pF 5 - 14 - - - - - ns

L

C

= 50pF 6 - - 23 - 29 - 35 ns

L

= 50pF 2 - - 60 - 75 - 90 ns

4.5 - - 12 - 15 - 18 ns

6 - - 10 - 13 - 15 ns
Input Capacitance C
Three-State Output

Capacitance
Power Dissipation Capacitance

C

(Notes 4, 5) (540)
Power Dissipation Capacitance

C

I

C

O

PD

PD

CL = 50pF - 10 - 10 - 10 - 10 pF

- - 20 - 20 - 20 - 20 pF

CL = 15pF 5 - 50 - - - - - pF

CL = 15pF 5 - 48 - - - - - pF

(Notes 4, 5) (541)

HCT TYPES

Propagation Delay t

PHL,tPLH

Data to Outputs (540) CL = 50pF 4.5 - - 24 - 30 - 36 ns

C

= 15pF 5 - 9 - - - - - ns

L

Data to Outputs (541) t

Output Enable and Disable

PHL,tPLH

t

PLZ,tPHZ

to Outputs (540, 541)

Output Transition Time t

TLH

Input Capacitance C

, t

I

CL = 50pF 4.5 - - 28 - 35 - 42 ns

= 15pF 5 - 11 - - - - - ns

C

L

CL = 50pF 4.5 - - 35 - 44 - 53 ns
C

= 15pF 5 - 14 - - - - - ns

L

THLCL

= 50pF 4.5 - - 12 - 15 - 18 ns

CL = 50pF - 10 - 10 - 10 - 10 pF

UNITSMIN TYP MAX MIN MAX MIN MAX

5

CD74HC540, CD74HCT540, CD74HC541, CD74HCT541

Switching Specifications C

= 50pF, Input tr, tf= 6ns (Continued)

L

PARAMETER SYMBOL

Three-State Output

C

O

Capacitance
Power Dissipation Capacitance

C

PD

(Notes 4, 5) (540, 541)

NOTES:

4. C

is used to determine the dynamic power consumption, per channel.

PD

5. PD = V

2

fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

CC

Test Circuits and Waveforms

tr = 6ns tf = 6ns

t

PHL

90%
50%
10%

t

10%

PLH

INPUT

t

INVERTING

OUTPUT

THL

TEST

CONDITIONS V

CC

(V)

25

o

C

-40oC TO
85oC

-55oC TO
125oC

- - 20 - 20 - 20 - 20 pF

CL = 15pF 5 - 55 - - - - - pF

= 6ns

t

PLH

t

f

1.3V

10%

90%

t

3V

GND

TLH

90%

50%

t

TLH

V

CC

GND

tr = 6ns

INPUT

t

INVERTING

OUTPUT

THL

t

2.7V

1.3V

0.3V

PHL

UNITSMIN TYP MAX MIN MAX MIN MAX

FIGURE 1. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

6ns 6ns

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

50%

t

t

OUTPUTS
ENABLED

PLZ

PHZ

10%

90%

90%

10%

t

PZL

t

PZH

OUTPUTS

DISABLED

50%

50%

FIGURE 3. HC THREE-STATEPROPAGATION DELAY

WAVEFORM

V

CC

GND

OUTPUTS
ENABLED

FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

t

0.3

t

PZL

PZH

6ns

1.3V

1.3V
OUTPUTS

ENABLED

t

r

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

t

t

OUTPUTS
ENABLED

6ns t

PLZ

PHZ

10%

90%

f

2.7

1.3

OUTPUTS

DISABLED

FIGURE 4. HCT THREE-STATEPROPAGATION DELAY

WAVEFORM

3V

GND

6

Test Circuits and Waveforms

(Continued)

NOTE: Opendrain waveforms t
VCC, CL = 50pF.

FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

TIED HIGH

and t

PLZ

OTHER

INPUTS

OR LOW

OUTPUT

DISABLE

PZL

IC WITH

THREE-

STATE

OUTPUT

OUTPUT

= 1kΩ

R

L

C

L

50pF

VCC FOR t
GND FOR t

PLZ

PHZ

AND t

AND t

PZL

PZH

are the sameas those for three-state shown on the left. Thetest circuit is Output RL=1kΩto

7

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