CD74HC4060,
[ /Title
(CD74
HC406
0,
CD74
HCT40
60)
Subect
(High
Speed
CMOS
Data sheet acquired from Harris Semiconductor
SCHS207
February 1998
Features
• Onboard Oscillator
• Common Reset
• Negative Edge Clocking
• Typical f
T
= 25oC
A
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
at VCC = 5V
= 50MHz at VCC = 5V, CL = 15pF,
MAX
= 30%, NIH = 30% of V
IL
o
CD74HCT4060
High Speed CMOS Logic
14-Stage Binary Counter with Oscillator
C to 125oC
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), VIH = 2V (Min)
IL
- CMOS Input Compatibility, I
≤ 1µA at VOL, V
l
Pinout
CD74HC4060, CD74HCT4060
(PDIP, SOIC)
TOP VIEW
Q12
Q13
Q14
Q6
Q5
Q7
Q4
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
Q10
Q8
Q9
MR
φI
φO
φO
OH
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1998
1
File Number 1654.1
CD74HC4060, CD74HCT4060
Description
The Harris CD74HC4060 and CD74HCT4060 each consist
of an oscillator section and 14 ripple-carry binary counter
stages. The oscillator configuration allows design of either
RC or crystal oscillator circuits. A Master Reset input is
provided which resets the counter to the all-0’s state and
disables the oscillator. A high level on the MR line
accomplishes the reset function. All counter stages are
master-slave flip-flops. The state of the counter is advanced
one step in binary order on the negative transition of φI (and
φO). All inputs and outputs are buffered. Schmitt trigger
action on the input-pulse-line permits unlimited rise and fall
times.
In order to achieve a symmetrical waveform in the oscillator
section the HCT4060 input pulse switch points are the same
as in the HC4060; only the MR input in the HCT4060 has
Functional Diagram
12
MR
14-STAGE
COUNTER
11
φI
OSCILLATOR
TTL switching levels.
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE
CD74HC4060E -55 to 125 16 Ld PDIP E16.3
CD74HCT4060E -55 to 125 16 Ld PDIP E16.3
CD74HC4060M -55 to 125 16 Ld SOIC M16.15
CD74HCT4060M -55 to 125 16 Ld SOIC M16.15
NOTES:
1. When ordering, use the entire partnumber. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
7
Q4
5
Q5
4
Q6
6
Q7
14
RIPPLE
AND
Q8
13
Q9
15
Q10
1
Q12
2
Q13
3
Q14
PKG.
NO.
φO
φO
9
10
GND = 8
V
= 16
CC
2
øO
øO
ø1
MR
CD74HC4060, CD74HCT4060
9
ø1Q1
10
11
FF1
ø1 Q1
R
12
FIGURE 1. LOGIC BLOCK DIAGRAM
TRUTH TABLE
ø4Q4
FF4
ø4 Q4
R
Q13
ø14 Q14
FF14
ø14 Q14
R
Q14
ø5 Q13
FF5 - FF13
ø5 Q13
R
723
5, 4, 6, 14, 13, 15, 1
Q4
Q5 - Q10, Q12
øI MR OUTPUT STATE
↑ L No Change
↓ L Advance to Next State
X H All Outputs are Low
3