CD54HCT4017
DECADE COUNTER/DIVIDER
WITH TEN DECODED OUTPUTS
SGDS012 – MAY 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
4.5-V to 5.5-V Operation
D
Fully Static Operation
D
Buffered Inputs
D
Common Reset
D
Positive-Edge Clocking
D
Balanced Propagation Delay and Transition
Times
D
Direct LSTTL Input Logic Compatibility
– V
IL
= 0.8 V Maximum; VIH = 2 V Minimum
D
CMOS Input Compatibility
– I
I
≤ 1 µA at VOL, V
OH
D
Packaged in Ceramic (F) DIP Packages and
Also Available in Chip Form (H)
description
The CD54HCT4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs.
Each decoded output normally is low and sequentially goes high on the low-to-high transition of the clock (CP)
input. Each output stays high for one clock period of the ten-clock-period cycle. The terminal count (TC) output
transitions low to high after output ten (9) goes low, and can be used in conjunction with the clock enable (CE
)
input to cascade several stages. CE
disables counting when in the high state. The master reset (MR) input, when
taken high, sets all the decoded outputs, except 0, to low.
The CD54HCT4017 is characterized for operation over the full military temperature range of –55°C to 125°C.
FUNCTION TABLE
INPUTS
CP CE MR
OUTPUT STATE
†
L X L No change
X H L No change
X XH
0 = H
1–9 = L
↑ L L Increments counter
↓ X L No change
X ↑ L No change
H ↓ L Increments counter
†
If n < 5, TC = H; otherwise, TC = L.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
5
1
0
2
6
7
3
GND
V
CC
MR
CP
CE
TC
9
4
8
F PACKAGE
(TOP VIEW)
CD54HCT4017
DECADE COUNTER/DIVIDER
WITH TEN DECODED OUTPUTS
SGDS012 – MAY 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
0
1
2
3
4
5
6
7
8
9
TC
Decoded Decimal Out
MR
Q
Q
CP
CE
Q
Q
Q
Q
Q
Q
Q
Q
15
13
14
3
2
4
7
10
1
5
6
9
11
12
D
C
R
D
C
R
D
C
R
D
C
R
D
C
R
CD54HCT4017
DECADE COUNTER/DIVIDER
WITH TEN DECODED OUTPUTS
SGDS012 – MAY 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(VI < 0 V or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(VO < 0 V or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, each output pin, I
O
(VO > 0 V or VO < VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . .
V
CC
or ground current, ICC ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions (see Note 1)
MIN MAX UNIT
V
CC
Supply voltage 4.5 5.5 V
V
IH
High-level input voltage VCC = 4.5 V to 5.5 V 2 V
V
IL
Low-level input voltage VCC = 4.5 V to 5.5 V 0.8 V
V
I
Input voltage 0 V
CC
V
V
O
Output voltage 0 V
CC
V
VCC = 2 V 0 1000
t
t
Input transition (rise and fall) time
VCC = 4.5 V 0 500
ns
VCC = 6 V 0 400
T
A
Operating free-air temperature –55 125 °C
NOTE 1: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to TI application report
Implications
of Slow or Floating CMOS Inputs
, literature number SCBA004.
CD54HCT4017
DECADE COUNTER/DIVIDER
WITH TEN DECODED OUTPUTS
SGDS012 – MAY 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP MAX
MIN
MAX
UNIT
CMOS loads VI = VIH or VIL, IO = –0.02 mA 4.5 V 4.4 4.4
V
OH
TTL loads VI = VIH or VIL, IO = –4 mA 4.5 V 3.98 3.7
V
CMOS loads VI = VIH or VIL, IO = 0.02 mA 4.5 V 0.1 0.1
V
OL
TTL loads VI = VIH or V
IL,
IO = 4 mA 4.5 V 0.26 0.4
V
I
I
VI = VCC to 0 5.5 V ±100 ±1000 nA
I
CC
VI = VCC or 0 5.5 V 8 160 µA
∆I
CC
†
VI = VCC to 2.1 V, IO = 0 4.5 to 5.5 V 100 360 490 µA
C
i
10 10 pF
†
For dual-supply systems, theoretical worst case (VI = 2.4 V, VCC = 5.5 V) specification is 1.8 mA.
INPUT LOADING
INPUT
UNIT LOAD
CP 0.15
CE 0.25
MR 0.3
Unit load is ∆ICC limit, e.g.,
360 µA MAX at TA = 25°C.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C
PARAMETER
V
CC
MIN MAX
MIN
MAX
UNIT
f
clock
Maximum clock frequency 4.5 V 25 17 MHz
CP 4.5 V 16 24
twPulse duration
MR 4.5 V 16 24
ns
t
su
Setup time, CE to CP 4.5 V 15 22 ns
t
h
Hold time, CE to CP 4.5 V 0 0 ns
t
rem
Removal time, MR 4.5 V 5 5 ns
CD54HCT4017
DECADE COUNTER/DIVIDER
WITH TEN DECODED OUTPUTS
SGDS012 – MAY 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements
TC
CP
MR
CE
0
1
2
3
4
5
6
7
8
9
0
1
2
1
2
3
4
5
6
7
8
9
CD54HCT4017
DECADE COUNTER/DIVIDER
WITH TEN DECODED OUTPUTS
SGDS012 – MAY 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics, CL = 50 pF, TA = 25°C (see Figures 1 and 2)
PARAMETER
FROM
TO
V
TA = 25°C
TA = –55°C
TO 125°C
UNIT
(INPUT)
(OUTPUT)
CC
MIN MAX MIN MAX
f
max
4.5 V 25 17 MHz
t
PLH
Any output
46 69
t
PHL
CP
TC
4.5 V
46 69
ns
t
PLH
Any output
50 75
t
PHL
CE
TC
4.5 V
50 75
ns
t
PLH
Any output
46 69
t
PHL
MR
TC
4.5 V
46 69
ns
t
THL
Any output
15 22
t
TLH
TC
4.5 V
15 22
ns
operating characteristics
PARAMETER TEST CONDITIONS TYP UNIT
C
pd
Power dissipation capacitance No load 39 pF
CD54HCT4017
DECADE COUNTER/DIVIDER
WITH TEN DECODED OUTPUTS
SGDS012 – MAY 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
t
h
t
su
50% V
CC
50%50%
10%10%
90% 90%
V
CC
V
CC
0 V
0 V
t
r
t
f
Reference
Input
Data
Input
50% V
CC
High-Level
Pulse
50% V
CC
V
CC
0 V
V
CC
0 V
t
w
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
50% V
CC
50%50%
10%10%
90% 90%
V
CC
V
OH
V
OL
0 V
t
r
t
f
Input
In-Phase
Output
50% V
CC
t
PLH
t
PHL
50% 50%
10% 10%
90%90%
V
OH
V
OL
t
r
t
f
t
PHL
t
PLH
Out-of-
Phase
Output
50% V
CC
10%
90%
V
CC
≈ V
CC
V
OL
0 V
Output
Control
Output
Waveform 1
(See Note B)
50% V
CC
t
PZL
t
PLZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
V
OH
≈ 0 V
50%
50%
t
PZH
t
PHZ
Output
Waveform 2
(See Note B)
≈ V
CC
Test
Point
From Output
Under Test
V
CC
S1
S2
LOAD CIRCUIT
PARAMETER
t
PZH
tpd or t
t
t
dis
t
en
t
PZL
t
PHZ
t
PLZ
Open Closed
S1
Closed Open
S2
Open Closed
Closed Open
Open Open
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily . All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
C
L
(see Note A)
50% V
CC
50% V
CC
1 kΩ
Figure 1. Load Circuit and Voltage Waveforms
CD54HCT4017
DECADE COUNTER/DIVIDER
WITH TEN DECODED OUTPUTS
SGDS012 – MAY 1999
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Input
Level
GND
t
PHL
t
r
V
S
CP
0–9
Input
Level
GND
t
PLH
MR
V
S
t
PLH
t
w
1–9
0, TC
TC
Input
Level
GND
CP
t
w
V
S
V
S
V
S
Input
Level
GND
CE
t
PLH
0–9
V
S
CE
t
su
V
S
Input
Level
GND
CE
t
PHL
TC
t
PLH
V
S
V
S
t
w
GND
Input
Level
Input
Level
GND
CP
Input
Level
GND
CP
t
rem
V
S
V
S
t
su
MR
CE
V
S
GND
Input
Level
GND
Input
Level
V
S
0.5 V
CC
INPUT LEVEL V
CC
t
PHL
V
S
V
S
V
S
V
S
1
f
max
t
PLH
t
PHL
t
PLH
t
h
t
f
Figure 2. Voltage Waveforms
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
Loading...