Texas Instruments CD54HCT4017F3A Datasheet
CD54HCT4017
DECADE COUNTER/DIVIDER
WITH TEN DECODED OUTPUTS
SGDS012 – MAY 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
4.5-V to 5.5-V Operation
D
Fully Static Operation
D
Buffered Inputs
D
Common Reset
D
Positive-Edge Clocking
D
Balanced Propagation Delay and Transition
Times
D
Direct LSTTL Input Logic Compatibility
– V
IL
= 0.8 V Maximum; VIH = 2 V Minimum
D
CMOS Input Compatibility
– I
I
≤ 1 µA at VOL, V
OH
D
Packaged in Ceramic (F) DIP Packages and
Also Available in Chip Form (H)
description
The CD54HCT4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs.
Each decoded output normally is low and sequentially goes high on the low-to-high transition of the clock (CP)
input. Each output stays high for one clock period of the ten-clock-period cycle. The terminal count (TC) output
transitions low to high after output ten (9) goes low, and can be used in conjunction with the clock enable (CE
)
input to cascade several stages. CE
disables counting when in the high state. The master reset (MR) input, when
taken high, sets all the decoded outputs, except 0, to low.
The CD54HCT4017 is characterized for operation over the full military temperature range of –55°C to 125°C.
FUNCTION TABLE
INPUTS
CP CE MR
OUTPUT STATE
†
L X L No change
X H L No change
X XH
0 = H
1–9 = L
↑ L L Increments counter
↓ X L No change
X ↑ L No change
H ↓ L Increments counter
†
If n < 5, TC = H; otherwise, TC = L.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
5
1
0
2
6
7
3
GND
V
CC
MR
CP
CE
TC
9
4
8
F PACKAGE
(TOP VIEW)
CD54HCT4017
DECADE COUNTER/DIVIDER
WITH TEN DECODED OUTPUTS
SGDS012 – MAY 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
0
1
2
3
4
5
6
7
8
9
TC
Decoded Decimal Out
MR
Q
Q
CP
CE
Q
Q
Q
Q
Q
Q
Q
Q
15
13
14
3
2
4
7
10
1
5
6
9
11
12
D
C
R
D
C
R
D
C
R
D
C
R
D
C
R
CD54HCT4017
DECADE COUNTER/DIVIDER
WITH TEN DECODED OUTPUTS
SGDS012 – MAY 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(VI < 0 V or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(VO < 0 V or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, each output pin, I
O
(VO > 0 V or VO < VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . .
V
CC
or ground current, ICC ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions (see Note 1)
MIN MAX UNIT
V
CC
Supply voltage 4.5 5.5 V
V
IH
High-level input voltage VCC = 4.5 V to 5.5 V 2 V
V
IL
Low-level input voltage VCC = 4.5 V to 5.5 V 0.8 V
V
I
Input voltage 0 V
CC
V
V
O
Output voltage 0 V
CC
V
VCC = 2 V 0 1000
t
t
Input transition (rise and fall) time
VCC = 4.5 V 0 500
ns
VCC = 6 V 0 400
T
A
Operating free-air temperature –55 125 °C
NOTE 1: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to TI application report
Implications
of Slow or Floating CMOS Inputs
, literature number SCBA004.
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