Texas Instruments CD74HCT393M96, CD74HCT393M, CD74HCT393E, CD74HC393M96, CD74HC393M Datasheet
...
CD74HC393,
CD74
C393
D74
CT39
)
Subect
High
peed
MOS
Data sheet acquired from Harris Semiconductor
SCHS186
September 1997
Features
• Fully Static Operation
• Buffered Inputs
• Common Reset
• Negative-Edge Clocking
• Typical f
T
= 25oC
A
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High NoiseImmunity: N
= 60 MHz at VCC = 5V, CL = 15pF,
MAX
= 30%, NIH= 30%of VCCat
IL
o
C to 125oC
CD74HCT393
High Speed CMOS Logic
Dual 4 -Stage Binary Counter
V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), VIH = 2V (Min)
IL
- CMOS Input Compatibility, I
Description
The Harris CD74HC393 and CD74HCT393 are 4-stage
ripple-carry binary counters. Al counter stages are masterslave flip-flops. The state of the stage advances one count
on the negative transition of each clock pulse; a high voltage
level on the MR line resets all counters to their zero state. All
inputs and outputs are buffered.
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE
CD74HC393E -55 to 125 14 Ld PDIP E14.3
CD74HCT393E -55 to 125 14 Ld PDIP E14.3
≤ 1µA at VOL, V
l
OH
PKG.
NO.
Pinout
CD74HC393, CD74HCT393
(PDIP, SOIC)
TOP VIEW
1CP
1MR
1Q0
1Q1
1Q2
1Q3
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
2CP
2MR
2Q0
2Q1
2Q2
2Q3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1997
1
File Number 1653.1
Functional Diagram
CD74HC393, CD74HCT393
3
1Q
1
CP
1
1MR
CP
2
2MR
2
13
12
BINARY
COUNTER
BINARY
COUNTER
TRUTH TABLE
OUTPUTS
CP COUNT
Q
0
Q
1
0LLLL
1HLLL
2LHLL
3HHLL
4LLHL
5HLHL
6LHHL
7HHHL
8LLLH
9HLLH
10LHLH
11 H H L H
12 L L H H
13 H L H H
14LHHH
15HHHH
4
1Q
5
1Q
6
1Q
11
2Q
10
2Q
9
2Q
8
2Q
GND = 7
V
CC
= 14
Q
2
0
1
2
3
0
1
2
3
Q
3
CP COUNT MR OUTPUT
↑ L No Change
↓ L Count
X H L L L L
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,
↑ = Transition from Low to High Level, ↓ = Transition from High to Low.
2
Logic Diagram
CD74HC393, CD74HCT393
CP
MR
1(13)
2(12)
Q
Φ
Q
Φ
R
3(11) 4(10) 5(9) 6(8)
Q
0
Q
ΦΦΦ
Q
ΦΦΦ
R R R
Q
1
Q
Q
Q
2
Q
Q
Q
3
3
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