Texas Instruments CD74HCT377M, CD74HCT377E, CD74HC377M96, CD74HC377M, CD74HC377E Datasheet
...
CD74HC377,
/
j
[ /Title
(CD74
HC377
,
CD74
HCT37
7)
Subect
(High
Speed
CMOS
Logic
Octal
DType
Flip-
Data sheet acquired from Harris Semiconductor
SCHS184
September 1997
Features
• Buffered Common Clock
• Buffered Inputs
• Typical Propagation Delay = 17ns at C
V
= 5V, TA = 25oC
CC
= 15pF,
L
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High NoiseImmunity: N
= 30%, NIH= 30%of VCCat
IL
Pinout
Octal D-Type Flip-Flop with Data Enable
V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
- CMOS Input Compatibility, I
Description
The Harris CD74HC377 and CD74HCT377 are octal D-type
C to 125oC
CD74HC377, CD74HCT377
flip-flops with a buffered clock (CP) common to all eight flipflops. All the flip-flops are loaded simultaneously on the
positive edge of the clock (CP) when the Data Enable (
Low.
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE
CD74HC377E -55 to 125 20 Ld PDIP E20.3
(PDIP, SOIC)
TOP VIEW
CD74HCT377
High Speed CMOS Logic
= 5V
= 0.8V (Max), VIH = 2V (Min)
l
≤ 1µA at VOL, V
OH
E) is
PKG.
NO.
Q
D
D
Q
Q
D
D
Q
GND
1
E
2
0
3
0
4
1
5
1
6
2
7
2
8
3
9
3
10
V
20
CC
Q
19
7
D
18
7
D
17
6
Q
16
6
Q
15
5
D
14
5
D
13
4
12
Q
4
11
CP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1997
1
File Number 1675.1
Functional Diagram
CD74HC377, CD74HCT377
3
D
0
4
D
1
7
D
2
8
D
3
13
D
4
14
D
5
17
D
6
18
D
7
CP
E
11 1
2
Q
5
Q
6
Q
9
Q
12
Q
15
Q
16
Q
19
Q
GND = 10
V
= 20
CC
0
1
2
3
4
5
6
7
TRUTH TABLE
INPUTS OUPUTS
OPERATING MODE
CP
ED
n
Q
n
Load “1” ↑ lh H
Load “0” ↑ ll L
Hold (Do Nothing) ↑ h X No Change
X H X No Change
NOTES:
H = High Voltage Level Steady State.
h = High Voltage Level One Set-up Time Prior to the Low to High Clock Transition.
L = Low Voltage Level Steady State.
l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition.
X = Don’t Care.
↑ = Low to High Clock Transition.
Logic Diagram
E
CP
D
0
CP
D
1
QD
Q
0
CP
D
2
QD
Q
1
CP
D
3
QD
Q
2
CP
D
4
QD
Q
3
CP
D
5
QD
Q
4
CP
D
6
QD
Q
5
CP
D
7
QD
Q
QD
CP
6
Q
7
2
CD74HC377, CD74HCT377
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, I
O
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, I
CC orIGND
. . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, V
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
CC
Thermal Resistance (Typical, Note 3) θJA (oC/W)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CC
DC Electrical Specifications
PARAMETER SYMBOL
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
V
IH
V
IL
V
OH
V
OL
I
I
I
CC
TEST
CONDITIONS
(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
I
V
CC
(V)
o
C -40oC TO 85oC -55oCTO125oC
25
UNITSV
- - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
- - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
- - ---- - - - V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
- - ---- - - - V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
VCC or
-6--±0.1 - ±1-±1µA
GND
VCC or
0 6 - - 8 - 80 - 160 µA
GND
3
Loading...