Texas Instruments CD74HCT283M96, CD74HCT283M, CD74HCT283E, CD74HC283M, CD74HC283E Datasheet

Data sheet acquired from Harris Semiconductor

/
j

SCHS176

November 1997

CD74HC283,

CD74HCT283

High Speed CMOS Logic

4-Bit Binary Full Adder with Fast Carry

[ /Title
(CD74
HC283
,
CD74
HCT28

3)
Sub­ect

(High
Speed
CMOS
Logic
4-Bit
Binary
Full
Adder

Features

• Adds Two Binary Numbers

• Full Internal Lookahead

• Fast Ripple Carry for Economical Expansion

• Operates with Both Positive and Negative Logic

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, NIH = 30% of V

IL

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

≤ 1µA at VOL, V

l

o

C to 125oC

OH

Description

The Harris CD74HC283 and CD74HCT283 binary full
adders that add two 4-bit binary numbers and generate a
carry-out bit if the sum exceeds 15.

Because of the symmetry of the add function, this device
can be used with either all active-high operands (positive
logic) or with all active-low operands (negative logic). When
using positive logicthe carry-in input must be tied low if there
is no carry-in.

Ordering Information

PART NUMBER TEMP. RANGE (oC) PACKAGE

CD74HC283E -55 to 125 16 Ld PDIP E16.3
CD74HCT283E -55 to 125 16 Ld PDIP E16.3
CD74HC283M -55 to 125 16 Ld SOIC M16.15

CC

CD74HCT283M -55 to 125 16 Ld SOIC M16.15

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer and die is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.

PKG.

NO.

Pinout

CD74HC283, CD74HCT283

(PDIP, SOIC)

TOP VIEW

16

1

S1

2

B1

3

A1

4

S0

5

A0

6

B0

7

C

IN

8

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

V

CC

15

B2

14

A2

13

S2

12

A3
B3

11
10

S3

9

C

OUT

Functional Diagram

5

A0

6

B0

3

A1

2

B1

14

A2

15

B2

12

A3

11

B3

7

C

IN

1

4

S0

1

S1

13

S2

10

S3

9

C

OUT

GND = 8

= 16

V

CC

File Number 1848.1

CD74HC283, CD74HCT283

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

V

IH

V

IL

V

OH

V

OL

I

I

I

CC

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

CC

(V)

o

C -40oC TO 85oC -55oC TO 125oC

25

UNITSV

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - - V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

VCC or

0 6 - - 8 - 80 - 160 µA

GND

2

CD74HC283, CD74HCT283

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

HCT Types
High Level Input

Voltage
Low Level Input

V

IH

V

IL

Voltage
High Level Output

Voltage

V

OH

CMOS Loads
High Level Output

V

OH

Voltage
TTL Loads

Low Level Output
Voltage

V

OL

CMOS Loads
Low Level Output

Voltage

V

OL

TTL Loads
Input Leakage

Current
Quiescent Device

I

I

ICC V

Current
Additional Quiescent

∆I

CC

Device Current Per
Input Pin: 1 Unit Load
(Note 4)

NOTE:

4. For dual-supply systems theoretical worst case (V

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

- - 4.5 to

- - 4.5 to

VILor V

IH

VILor V

IH

VIHor V

IL

VIHor V

IL

VCC to

GND

or

CC

GND

V

CC

-2.1

o

C -40oC TO 85oC -55oC TO 125oC

V

CC

(V)

25

UNITSV

2--2- 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

- 4.5 4.4 - - 4.4 - 4.4 - V

- 4.5 3.98 - - 3.84 - 3.7 - V

- 4.5 - - 0.1 - 0.1 - 0.1 V

- 4.5 - - 0.26 - 0.33 - 0.4 V

- 5.5 - - ±0.1 - ±1-±1 µA

- 5.5 - - 8 - 80 - 160 µA

- 4.5 to

- 100 360 - 450 - 490 µA

5.5

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

HCT Input Loading Table

INPUT UNIT LOADS

C

IN

B1, A1, A0 1

B0 0.4

B3, A3, A2, B2 0.5

NOTE: Unit Load is ∆ICClimit specified in DC Electrical
Specifications table, e.g., 360µA max at 25oC.

Switching Specifications Input t

r

PARAMETER SYMBOL

HC TYPES

Propagation Delay t

PLH,tPHL

CIN to S0 4.5 - - 32 - 40 - 48 ns

1.5

, tf = 6ns

TEST

CONDITIONS V

CC

(V)

25oC

-40oC TO
85oC

-55oC TO
125oC

CL= 50pF 2 - - 160 - 200 - 240 ns

CL= 15pF 5 - 13 - - - - - ns
CL= 50pF 6 - - 27 - 34 - 41 ns

UNITSMIN TYP MAX MIN MAX MIN MAX

3

CD74HC283, CD74HCT283

Switching Specifications Input t

PARAMETER SYMBOL

CIN to S1 t

CIN to S2, CIN to C

OUT

CIN to S3 t

An, Bn to C

OUT

An, Bn to Sn t

Output Transition Time t

Input Capacitance C
Power Dissipation

Capacitance, (Notes 5, 6)

HCT TYPES

Propagation Delay

CIN to S0 t

CIN to S1 t

CIN to S2, CIN to C

OUT

CIN to S3 t

An, Bn to C

OUT

An, Bn to Sn t

Output Transition Time t

PLH,tPHL

t

PLH,tPHL

PLH,tPHL

t

PLH,tPHL

PLH,tPHL

TLH

C

PLH

PLH

t

PLH

PLH

t

PLH,tPH

PLH

TLH

, tf = 6ns (Continued)

r

TEST

25oC

-40oC TO
85oC

-55oC TO
125oC

CONDITIONS VCC(V)

CL= 50pF 2 - - 180 - 225 - 270 ns

4.5 - - 36 - 45 - 54 ns
CL= 15pF 5 - 15 - - - - - ns
CL= 50pF 6 - - 31 - 38 - 46 ns
CL= 50pF 2 - - 195 - 245 - 295 ns

4.5 - - 39 - 49 - 59 ns
CL= 15pF 5 - 16 - - - - - ns
CL= 50pF 6 - - 33 - 42 - 50 ns
CL= 50pF 2 - - 230 - 290 - 345 ns

4.5 - - 46 - 58 - 69 ns
CL= 15pF 5 - 19 - - - - - ns
CL= 50pF 6 - - 39 - 49 - 59 ns
CL= 50pF 2 - - 195 - 245 - 295 ns

4.5 - - 39 - 49 - 59 ns
CL= 15pF 5 - 16 - - - - - ns
CL= 50pF 6 - - 33 - 42 - 50 ns
CL= 50pF 2 - - 210 - 265 - 315 ns

4.5 - - 42 - 53 - 63 ns
CL= 15pF 5 - 18 - - - - - ns
CL= 50pF 6 - - 36 - 45 - 54 ns

, t

CL= 50pF 2 - - 75 - 95 - 110 ns

THL

4.5 - - 15 - 19 - 22 ns

6 - - 13 - 16 - 19 ns

IN

PD

, t

CL= 50pF - - - 10 - 10 - 10 pF

-5-70-----pF

CL= 15pF 5 - 13 - - - - - ns

PHL

CL= 50pF 4.5 - - 31 - 39 - 47 ns

, t

CL= 15pF 5 - 18 - - - - - ns

PHL

CL= 50pF 4.5 - 43 - 54 - 65 ns

, t

CL= 15pF 5 - 19 - - - - - ns

PHL

CL= 50pF 4.5 - 46 - 58 - 69 ns

, t

CL= 15pF 5 - 22 - - - - - ns

PHL

CL= 50pF 4.5 - 53 - 66 - 80 ns

LCL= 15pF 5 - 20 - - - - - ns

CL= 50pF 4.5 - 48 - 60 - 72 ns

, t

CL= 15pF 5 - 21 - - - - - ns

PHL

CL= 50pF 4.5 - 49 - 61 - 74 ns

, t

CL= 50pF 4.5 - 15 - 19 - 22 ns

THL

UNITSMIN TYP MAX MIN MAX MIN MAX

4

CD74HC283, CD74HCT283

Switching Specifications Input t

, tf = 6ns (Continued)

r

TEST

PARAMETER SYMBOL

Input Capacitance C
Power Dissipation

C

CONDITIONS VCC(V)

IN

PD

- - - - 10 - 10 - 10 pF

-5-82-----pF

Capacitance, (Notes 5, 6)

NOTES:

5. CPD is used to determine the dynamic power consumption, per package.

6. PD = V

2

fi(CPD + CL) where: fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

CC

Test Circuits and Waveforms

tr = 6ns tf = 6ns

V

t

CC

GND

TLH

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

90%
50%
10%

t

90%

50%

10%

PLH

25oC

tr = 6ns

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

-40oC TO
85oC

2.7V

1.3V

0.3V

t

PLH

-55oC TO
125oC

= 6ns

t

f

90%

1.3V

10%

t

UNITSMIN TYP MAX MIN MAX MIN MAX

3V

GND

TLH

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

5

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