Texas Instruments CD74HCT14M96, CD74HCT14M, CD74HCT14E, CD74HC14M96, CD74HC14M Datasheet

Data sheet acquired from Harris Semiconductor

/

SCHS129

January 1998

CD74HC14,

CD74HCT14

High Speed CMOS Logic

Hex Inverting Schmitt Trigger

[ /Title
(CD74H
C14,
CD74H
CT14)

Subject
(High
Speed
CMOS
Logic
Hex
Invert-

Features

• Unlimited Input Rise and Fall Times

• Exceptionally High Noise Immunity

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, NIH = 30% of V

IL

o

C to 125oC

Pinout

CD54HC14, CD54HCT14, CD74HC14, CD74HCT14

(PDIP, CERDIP, SOIC)

1A

1
2

1Y

3

2A

4

2Y

5

3A

6

3Y

7

GND

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,
V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

≤ 1µA at VOL, V

l

Description

The Harris CD74HC14, CD74HCT14 each contain 6
inverting Schmitt Triggers in one package.

Ordering Information

TEMP. RANGE

CC

TOP VIEW

PART NUMBER

CD54HCT14F -55 to 125 14 Ld CERDIP F14.3

14

V

CC

6A

13
12

6Y
5A

11

5Y

10

4A

9

4Y

8

(oC) PACKAGE

OH

PKG.

NO.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

1

File Number 1781.1

Functional Diagram

CD74HC14, CD74HCT14

INPUT (A) OUTPUT (Y)

NOTE:
H= High Level
L= Low Level

1A

2A

3A

4A

5A

6A

1

3

5

9

11

13

2

1Y

4

2Y

6

3Y

8

4Y

10

5Y

12

6Y

GND = 7

= 14

V

CC

TRUTH TABLE

LH

HL

Logic Diagram

nA nY

2

CD74HC14, CD74HCT14

V

V

O

V

CC

V

I

GND

V

CC

V

O

GND

FIGURE 3. HYSTERESIS DEFINITION, CHARACTERISTIC, AND TEST SETUP

H

VH = VT+ - VT-

V

I

VT-VT+

+V

V

T

-

T

V

H

3