Texas Instruments CD74HCT423M96, CD74HCT423E, CD74HCT123M96, CD74HCT123M, CD74HCT123E Datasheet

Data sheet acquired from Harris Semiconductor

/
j

SCHS142

September 1997

CD74HC123, CD74HCT123,

CD74HC423, CD74HCT423

High Speed CMOS Logic Dual Retriggerable

Monostable Multivibrators with Resets

[ /Title
(CD74
HC123
,
CD74
HCT12
3,
CD74
HC423
,
CD74
HCT42

3)
Sub­ect

(High
Speed

Features

• Overriding Reset Terminates Output Pulse

• Triggering From the Leading or Trailing Edge

• Q and

• Separate Resets

• Wide Range of Output-Pulse Widths

• Schmitt Trigger on Both

• Fanout (Over Temperature Range)

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

• HC Types

• HCT Types

Q Buffered Outputs

A and B Inputs

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

o

C to 125oC

Logic ICs

- 2V to 6V Operation

- High NoiseImmunity: N
V

= 5V

CC

= 30%, NIH= 30%of VCCat

IL

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,
V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

≤ 1µA at VOL, V

l

OH

Description

The Harris CD74HC123, CD74HCT123, CD74HC423 and
CD74HCT423 are dual monostable multivibrators with
resets. They are all retriggerable and differ only in that the
123 types can be triggered by a negative to positive reset
pulse; whereas the 423 types do not have this feature. An
external resistor (R

) and an external capacitor (CX) control

X

the timing and the accuracy for the circuit. Adjustment of Rx
and C
the Q and

provides a wide range of output pulse widths from

X

Q terminals. Pulse triggering on the A and B
inputs occur at a particular voltage level and is not related to
the rise and fall times of the trigger pulses.

Once triggered, the output pulse width may be extended by
retriggering inputs

A and B. The output pulse can be
terminated by a LOW level on the Reset (R) pin. Trailing
edge triggering (

A) and leading edge triggering (B) inputs
are provided for triggering from either edge of the input
pulse. If either Mono is not used each input on the unused
device (

A, B, and R) must be terminated high or low.

The minimum value of external resistance, Rx is typically 5kΩ.
The minimum value external capacitance, C
calculation for the pulse width is t

= 0.45 RXCX at VCC = 5V.

W

, is 0pF. The

X

Ordering Information

PKG.

PART NUMBER TEMP. RANGE (oC) PACKAGE

CD74HC123E -55 to 125 16 Ld PDIP E16.3
CD74HCT123E -55 to 125 16 Ld PDIP E16.3

NO.

Pinout

CD74HC123, CD74HCT123, CD74HC423, CD74HCT423

(PDIP, SOIC)

TOP VIEW

16

1

1A

2

1B

3

1R

4

1Q

5

2Q

6

2C

X

2R

7

XCX

8

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

V

CC

15

1R

XCX

14

1C

X

13

1Q

12

2Q

11

2R

10

2B

9

2A

CD74HC423E -55 to 125 16 Ld PDIP E16.3
CD74HCT423E -55 to 125 16 Ld PDIP E16.3
CD74HC123M -55 to 125 16 Ld SOIC M16.15
CD74HCT123M -55 to 125 16 Ld SOIC M16.15
CD74HC423M -55 to 125 16 Ld SOIC M16.15
CD74HCT423M -55 to 125 16 Ld SOIC M16.15

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer ordiefor this partnumber is availablewhichmeets all elec­trical specifications. Please contact your local sales office or
Harris customer service for ordering information.

1

File Number 1708.1

CD74HC123, CD74HCT123, CD74HC423, CD74HCT423

Functional Diagram

1A

1B

1R

2R

2A

2B

14 15

1Cx 1RxCx

1

2

3

11

9

10

MONO 1

MONO 2

2Cx 2RxCx

67

1Cx 1Rx

2Cx 2Rx

V

13

4

5

12

V

TRUTH TABLE

INPUTS OUTPUTS

ABRQQ

CD74HC/HCT123

CC

1Q

1Q

2Q

2Q

CC

HXHLH
XLHLH

L ↑ H

↓ HH

XXLLH

LH↑

CD74HC/HCT423

HXHLH
XLHLH

L ↑ H

↓ HH

XXLLH

NOTE: H = High Voltage Level, L = Low Voltage Level,
X = Don’t Care.

2

CD74HC123, CD74HCT123, CD74HC423, CD74HCT423

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

V

IH

V

IL

V

OH

V

OL

I

I

I

CC

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

CC

(V)

o

25

C -40oC TO 85oC -55oC TO 125oC

UNITSV

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - - V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

VCC or

0 6 - - 8 - 80 - 160 µA

GND

3