Texas Instruments CD74HCT10M96, CD74HCT10M, CD74HCT10E, CD74HC10M96, CD74HC10M Datasheet
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CD74HC10,
/
j
/
/
[ /Title
(CD74
HC10,
CD74
HCT10
)
Sub-
ect
(High
Speed
CMOS
Logic
Triple
3-Input
NAND
Gate)
Autho
r ()
Keywords
(High
Speed
CMOS
Logic
Triple
3-Input
NAND
Gate,
High
Speed
CMOS
Logic
Triple
3-Input
NAND
Gate,
Harris
Semi-
Data sheet acquired from Harris Semiconductor
SCHS128
August 1997
Features
• Buffered Inputs
• Typical Propagation Delay: 8ns at V
C
= 15pF, TA = 25oC
L
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
= 30%, NIH = 30% of V
IL
CC
= 5V,
o
Pinout
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
- CMOS Input Compatibility, I
• Related Literature
- CD54HC10F3A and CD54HCT10F3A Military
C to 125oC
Description
The Harris CD74HC10, CD74HCT10, logic gates utilize
silicon gate CMOS technology to achieve operating speeds
similar to LSTTL gates with the low power consumption of
standard CMOS integrated circuits. All devices have the
ability to drive 10 LSTTL loads. The 74HCT logic family is
CC
CD74HC10, CD74HCT10
(PDIP, SOIC)
TOP VIEW
1A
1
2
1B
3
2A
4
2B
5
2C
2Y
6
GND
7
CD74HCT10
High Speed CMOS Logic
Triple 3-Input NAND Gate
at VCC = 5V
V
= 0.8V (Max), VIH = 2V (Min)
IL
≤ 1µA at VOL, V
l
Data Sheet, Document Number 3758
V
14
CC
1C
13
12
1Y
3C
11
3B
10
3A
9
3Y
8
OH
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1997
1
File Number 1551.1
Functional Diagram
CD74HC10, CD74HCT10
1A
1B
2A
2B
2C
2Y
GND
1
2
3
4
5
6
7
14
V
CC
13
1C
12
1Y
11
3C
10
3B
9
3A
8
3Y
TRUTH TABLE
INPUTS OUTPUT
nA nB nC nY
LLLH
LLHH
LHLH
Logic Symbol
LHHH
HLLH
HLHH
HHLH
HHHL
NOTE: H = High Voltage Level, L = Low Voltage Level
nA
nB
nC
nY
2
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