Texas Instruments CD74HCT03M96, CD74HCT03M, CD74HCT03E, CD74HC03M96, CD74HC03M Datasheet

CD74HC03,

/

[ /Title
(CD74H
C03,
CD74H
CT03)

Subject
(High
Speed
CMOS
Logic
Quad 2­Input

Data sheet acquired from Harris Semiconductor
SCHS126

February 1998

Features

• Buffered Inputs

• Typical Propagation Delay: 8ns at V
C

= 15pF, TA = 25oC

L

• Output Pull-up to 10V

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

CC

= 5V,

o

Quad 2-Input NAND Gate with Open Drain

C to 125oC

CC

OH

CD74HCT03

High Speed CMOS Logic

Description

The Harris CD74HC03 and CD74HCT03 logic gates utilize
silicon gate CMOS technology to achieve operating speeds
similar to LSTTL gates with the low power consumption of
standard CMOS integrated circuits. Alldevices havethe abil­ity to drive 10 LSTTL loads. The 74HCT logic family is func­tionally as well as pin compatible with the standard 74LS
logic family.

These open drain NAND gates can drive into resistive loads
to output voltages as high as 10V. Minimum values of R
required verses load voltage are shown in Figure 2.

Ordering Information

TEMP.RANGE

PART NUMBER

CD74HC03E -55 to 125 14 Ld PDIP E14.3
CD74HCT03E -55 to 125 14 Ld PDIP E14.3
CD74HC03M -55 to 125 14 Ld SOIC M14.15
CD74HCT03M -55 to 125 14 Ld SOIC M14.15

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact yourlocal salesoffice or
Harris customer service for ordering information.

(oC) PACKAGE

PKG.

NO.

L

Pinout

CD74HC03, CD74HCT03

(PDIP, SOIC)

TOP VIEW

1A

1
2

1B

3

1Y

4

2A

5

2B

6

2Y

7

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

14

V

CC

4B

13
12

4A
4Y

11

3B

10

3A

9

3Y

8

1

File Number 1832.1

Functional Diagram

CD74HC03, CD74HCT03

1

1A

2

1B

4

2A

5

2B

9

3A

10

3B

12

4A

13

4B

AB Y

L L Z (Note 4) H (Note 3)
H L Z (Note 4) H (Note 3)
L H Z (Note 4) H (Note 3)
HHLL

NOTES:

3. Requires pull-up (RL to VL)

4. Without pull-up (high impedance)

TRUTH TABLE

3

6

8

11

GND = 7
V

CC

1Y

2Y

3Y

4Y

= 14

Logic Symbol

nA

nB

nY

2