Texas Instruments CD74HCT86M96, CD74HCT86M, CD74HCT86E, CD74HC86M96, CD74HC86M Datasheet

CD74HC86,

/
j

[ /Title
(CD74
HC86,
CD74
HCT86
)

Sub-

ect
(High
Speed
CMOS
Logic
Quad
2-Input
EXCL
USIVE
OR

Data sheet acquired from Harris Semiconductor
SCHS137

August 1997

Features

• Typical Propagation Delay: 9ns at VCC = 5V,
C

= 15pF, TA = 25oC

L

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

o

Applications

• Logical Comparators

• Parity Generators and Checkers

• Adders and Subtractors

C to 125oC

CC

OH

CD74HCT86

High Speed CMOS Logic

Quad 2-Input EXCLUSIVE OR Gate

Description

The Harris CD74HC86, CD74HCT86 contain four
independent EXCLUSIVE OR gates in one package. They
provide the system designer with a means for
implementation of theEXCLUSIVE OR function. Logic gates
utilize silicon gate CMOS technology to achieve operating
speeds similar to LSTTL gates with the low power
consumption of standard CMOS integrated circuits. All
devices havethe ability to drive 10 LSTTL loads. The 74HCT
logic family is functionally pin compatible with the standard
74LS logic family.

Ordering Information

TEMP.RANGE

PART NUMBER

CD74HC86E -55 to 125 14 Ld PDIP E14.3
CD74HCT86E -55 to 125 14 Ld PDIP E14.3
CD74HC86M -55 to 125 14 Ld SOIC M14.15
CD74HCT86M -55 to 125 14 Ld SOIC M14.15
CD54HC86W -55 to 125 Wafer
CD54HCT86W -55 to 125 Wafer
CD54HC86H -55 to 125 Die

NOTE: Whenordering, use the entire part number.Addthe suffix 96
to obtain the variant in the tape and reel.

(oC) PACKAGE

PKG.

NO.

Pinout

CD74HC86, CD74HCT86

(PDIP, SOIC)

TOP VIEW

1A

1
2

1B

3

1Y

4

2A

5

2B

6

2Y

7

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

1

14

V

CC

4B

13
12

4A
4Y

11

3B

10

3A

9

3Y

8

File Number 1644.1

Functional Diagram

CD74HC86, CD74HCT86

1A

1B

1Y

2A

2B

2Y

GND

1

2

3

4

5

6

7

14

V

CC

13

4B

12

4A

11

4Y

10

3B

9

3A

8

3Y

TRUTH TABLE

INPUTS OUTPUT

nA nB nY

LLL
LHH
HLH

Logic Symbol

HHL

NOTE: H = High Voltage Level, L = Low Voltage Level

nA

nY

nB

2

CD74HC86, CD74HCT86

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 1) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

V

IH

V

IL

V

OH

V

OL

I

I

I

CC

TEST

CONDITIONS

25oC -40oC TO +85oC -55oC TO 125oC

VCC (V)

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIH or

V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

VCC or

0 6 - - 2 - 20 - 40 µA

GND

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

3

CD74HC86, CD74HCT86

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

VCC (V)

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

- - 4.5 to

5.5

V

IL

- - 4.5 to

5.5

V

OH

VIH or

V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

CMOS Loads
High Level Output

-4 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads

Low Level Output
Voltage

V

OL

VIH or

V

IL

-0.02 4.5 - - 0.1 - 0.1 - 0.1 V

CMOS Loads
Low Level Output

4 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads

Input Leakage
Current

I

I

V

CC

0 5.5 - ±0.1 - ±1-±1 µA

and

GND

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

CC

VCC or

0 5.5 - - 2 - 20 - 40 µA

GND

∆I

CC

V

CC

-2.1

- 4.5 to

5.5
Input Pin: 1 Unit Load
(Note 2)

NOTE:

2. For dual-supply systems theorectical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

25oC -40oC TO +85oC -55oC TO 125oC

2-- 2 - 2 - V

- - 0.8 - 0.8 - 0.8 V

- 100 360 - 450 - 490 µA

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

All 1

NOTE: Unit Load is ∆ICClimit specified in DC Electrical
Specifications table, e.g. 360µA max at 25oC.

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay,Input to
Output (Figure 1)

PropagationDelay,DataInputto
Output Y

Transition Times (Figure 1) t

t

PLH

t

PLH

TLH

, tf = 6ns

r

, t

PHLCL

, t

PHLCL

, t

THLCL

TEST

CONDITIONS

= 50pF 2 - - 120 - 150 - 180 ns

= 15pF 5 - 9 - ----ns

= 50pF 2 - - 75 - 95 - 110 ns

V

CC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

4.5 - - 24 - 30 - 36 ns
6 - - 20 - 26 - 31 ns

4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns

4

CD74HC86, CD74HCT86

Switching Specifications Input t

PARAMETER SYMBOL

Input Capacitance C
Power Dissipation Capacitance

, tf = 6ns (Continued)

r

TEST

CONDITIONS

I

C

PD

- - - - 10 - 10 - 10 pF

- 5-22-----pF

V

CC

(V)

(Notes 3, 4)

HCT TYPES

Propagation Delay, Input to

t

PLH

, t

PHLCL

= 50pF 4.5 - - 32 - 40 - 48 ns

Output (Figure 2)
PropagationDelay,DataInputto

t

PLH

, t

PHLCL

= 15pF 5 - 13 - ----ns

Output Y
Transition Times (Figure 2) t
Input Capacitance C
Power Dissipation Capacitance

TLH

, t

I

C

PD

THLCL

= 50pF 4.5 - - 15 - 19 - 22 ns

- - - - 10 - 10 - 10 pF

- 5-27-----pF

(Notes 3, 4)

NOTES:

3. CPD is used to determine the dynamic power consumption, per gate.

4. PD = V

2

fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

CC

Test Circuits and Waveforms

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

tr = 6ns tf = 6ns

V

t

CC

GND

TLH

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

90%
50%
10%

t

90%

50%

10%

PLH

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

= 6ns

t

PLH

t

f

1.3V

10%

90%

t

3V

GND

TLH

tr = 6ns

INPUT

t

INVERTING

OUTPUT

THL

t

2.7V

1.3V

0.3V

PHL

FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

5

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