CD74HC86,
[ /Title
(CD74
HC86,
CD74
HCT86
)
Sub-
ect
(High
Speed
CMOS
Logic
Quad
2-Input
EXCL
USIVE
OR
Data sheet acquired from Harris Semiconductor
SCHS137
August 1997
Features
• Typical Propagation Delay: 9ns at VCC = 5V,
C
= 15pF, TA = 25oC
L
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), VIH = 2V (Min)
IL
- CMOS Input Compatibility, I
= 30%, NIH = 30% of V
IL
≤ 1µA at VOL, V
l
o
Applications
• Logical Comparators
• Parity Generators and Checkers
• Adders and Subtractors
C to 125oC
CC
OH
CD74HCT86
High Speed CMOS Logic
Quad 2-Input EXCLUSIVE OR Gate
Description
The Harris CD74HC86, CD74HCT86 contain four
independent EXCLUSIVE OR gates in one package. They
provide the system designer with a means for
implementation of theEXCLUSIVE OR function. Logic gates
utilize silicon gate CMOS technology to achieve operating
speeds similar to LSTTL gates with the low power
consumption of standard CMOS integrated circuits. All
devices havethe ability to drive 10 LSTTL loads. The 74HCT
logic family is functionally pin compatible with the standard
74LS logic family.
Ordering Information
TEMP.RANGE
PART NUMBER
CD74HC86E -55 to 125 14 Ld PDIP E14.3
CD74HCT86E -55 to 125 14 Ld PDIP E14.3
CD74HC86M -55 to 125 14 Ld SOIC M14.15
CD74HCT86M -55 to 125 14 Ld SOIC M14.15
CD54HC86W -55 to 125 Wafer
CD54HCT86W -55 to 125 Wafer
CD54HC86H -55 to 125 Die
NOTE: Whenordering, use the entire part number.Addthe suffix 96
to obtain the variant in the tape and reel.
(oC) PACKAGE
PKG.
NO.
Pinout
CD74HC86, CD74HCT86
(PDIP, SOIC)
TOP VIEW
1A
1
2
1B
3
1Y
4
2A
5
2B
6
2Y
7
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1997
1
14
V
CC
4B
13
12
4A
4Y
11
3B
10
3A
9
3Y
8
File Number 1644.1
Functional Diagram
CD74HC86, CD74HCT86
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14
V
CC
13
4B
12
4A
11
4Y
10
3B
9
3A
8
3Y
TRUTH TABLE
INPUTS OUTPUT
nA nB nY
LLL
LHH
HLH
Logic Symbol
HHL
NOTE: H = High Voltage Level, L = Low Voltage Level
nA
nY
nB
2