TEXAS INSTRUMENTS CD54HC86 Technical data

Data sheet acquired from Harris Semiconductor

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SCHS137D

August 1997 - Revised September 2003

CD54HC86, CD74HC86,

CD54HCT86, CD74HCT86

High-Speed CMOS Logic

Quad 2-Input EXCLUSIVE-OR Gate

/Title
CD74

C86,
D74
CT86

Sub­ect
High

peed

MOS

ogic

uad

-Input
XCL

SIVE
R

Features

• Typical Propagation Delay: 9ns at VCC = 5V,
C

= 15pF, TA = 25oC

L

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

o

C to 125oC

OH

Applications

• Logical Comparators

• Parity Generators and Checkers

• Adders and Subtractors

Description

The ’HC86 and ’HCT86 contain four independent
EXCLUSIVE OR gates in one package. They provide the
system designer with a means for implementation of the
EXCLUSIVE OR function. Logic gates utilize silicon gate
CMOS technology to achieve operating speeds similar to
LSTTL gates with the low power consumption of standard
CMOS integratedcircuits. All devices have the ability to drive
10 LSTTL loads. The HCT logic family is functionally pin
compatible with the standard LS logic family.

Ordering Information

TEMP. RANGE

CC

PART NUMBER

CD54HC86F3A -55 to 125 14 Ld CERDIP
CD54HCT86F3A -55 to 125 14 Ld CERDIP
CD74HC86E -55 to 125 14 Ld PDIP
CD74HC86M -55 to 125 14 Ld SOIC
CD74HC86MT -55 to 125 14 Ld SOIC
CD74HC86M96 -55 to 125 14 Ld SOIC
CD74HCT86E -55 to 125 14 Ld PDIP
CD74HCT86M -55 to 125 14 Ld SOIC
CD74HCT86MT -55 to 125 14 Ld SOIC

(oC) PACKAGE

CD74HCT86M96 -55 to 125 14 Ld SOIC

NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of

250.

Pinout

CD54HC86, CD54HCT86

(CERDIP)

CD74HC86, CD74HCT86

(PDIP, SOIC)

TOP VIEW

1A

1
2

1B
1Y

3
4

2A

5

2B

6

2Y

7

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© 2003, Texas Instruments Incorporated

1

14

V

CC

4B

13
12

4A
4Y

11

3B

10

3A

9

3Y

8

Functional Diagram

CD54HC86, CD74HC86, CD54HCT86, CD74HCT86

1A

1B

1Y

2A

2B

2Y

GND

1

2

3

4

5

6

7

14

V

CC

13

4B

12

4A

11

4Y

10

3B

9

3A

8

3Y

TRUTH TABLE

INPUTS OUTPUT

nA nB nY

LLL
LHH
HLH

Logic Symbol

HHL

H = High Voltage Level, L = Low Voltage Level

nA

nY

nB

2

CD54HC86, CD74HC86, CD54HCT86, CD74HCT86

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

CC

Thermal Resistance (Typical, Note 1) θJA (oC/W)

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 80

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 86

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

V

IH

V

IL

V

OH

V

OL

I

I

I

CC

TEST

CONDITIONS

25oC -40oC TO +85oC -55oC TO 125oC

VCC (V)

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIH or

V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

VCC or

0 6 - - 2 - 20 - 40 µA

GND

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

3

CD54HC86, CD74HC86, CD54HCT86, CD74HCT86

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

VCC (V)

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

- - 4.5 to

5.5

V

IL

- - 4.5 to

5.5

V

OH

VIH or

V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

CMOS Loads
High Level Output

-4 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads

Low Level Output
Voltage

V

OL

VIH or

V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

CMOS Loads
Low Level Output

4 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads

Input Leakage
Current

I

I

V

CC

- 5.5 - ±0.1 - ±1-±1 µA

and

GND

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

CC

∆I

CC

(Note 2)

VCC or

GND

V

CC

- 2.1

0 5.5 - - 2 - 20 - 40 µA

- 4.5 to

5.5

Input Pin: 1 Unit Load

NOTE:

2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

25oC -40oC TO +85oC -55oC TO 125oC

2-- 2 - 2 - V

- - 0.8 - 0.8 - 0.8 V

- 100 360 - 450 - 490 µA

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

All 1

NOTE: Unit Load is ∆ICClimit specified in DC Electrical
Specifications table, e.g. 360µA max at 25oC.

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay,Input to
Output (Figure 1)

PropagationDelay,DataInputto
Output Y

Transition Times (Figure 1) t

Input Capacitance C

t

PLH

t

PLH

TLH

, tf = 6ns

r

, t

PHLCL

, t

PHLCL

, t

THLCL

I

TEST

CONDITIONS

= 50pF 2 - - 120 - 150 - 180 ns

= 15pF 5 - 9 - ----ns

= 50pF 2 - - 75 - 95 - 110 ns

V

CC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

4.5 - - 24 - 30 - 36 ns
6 - - 20 - 26 - 31 ns

4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns

- - - - 10 - 10 - 10 pF

4

CD54HC86, CD74HC86, CD54HCT86, CD74HCT86

Switching Specifications Input t

PARAMETER SYMBOL

Power Dissipation Capacitance

, tf = 6ns (Continued)

r

TEST

CONDITIONS

C

PD

- 5-22-----pF

V

CC

(V)

(Notes 3, 4)

HCT TYPES

Propagation Delay, Input to

t

PLH

, t

PHLCL

= 50pF 4.5 - - 32 - 40 - 48 ns

Output (Figure 2)
PropagationDelay,DataInputto

t

PLH

, t

PHLCL

= 15pF 5 - 13 - ----ns

Output Y
Transition Times (Figure 2) t
Input Capacitance C
Power Dissipation Capacitance

TLH

, t

I

C

PD

THLCL

= 50pF 4.5 - - 15 - 19 - 22 ns

- - - - 10 - 10 - 10 pF

- 5-27-----pF

(Notes 3, 4)

NOTES:

3. CPD is used to determine the dynamic power consumption, per gate.

4. PD = V

2

fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

CC

Test Circuits and Waveforms

tr = 6ns tf = 6ns

V

INPUT

90%
50%
10%

CC

GND

25oC -40oC TO 85oC -55oC TO 125oC

= 6ns

tr = 6ns

INPUT

2.7V

1.3V

0.3V

t

f

3V

GND

UNITSMIN TYP MAX MIN MAX MIN MAX

t

INVERTING

OUTPUT

THL

t

PHL

t

PLH

50%

10%

90%

t

TLH

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

t

INVERTING

OUTPUT

THL

t

PHL

t

PLH

1.3V

10%

90%

t

TLH

FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

5

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

5962-8984401CA ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type

CD54HC86F3A ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type

CD54HCT86F ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type

CD54HCT86F3A ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type

CD74HC86E ACTIVE PDIP N 14 25 Pb-Free

CD74HC86EE4 ACTIVE PDIP N 14 25 Pb-Free

CD74HC86M ACTIVE SOIC D 14 50 Green (RoHS &

CD74HC86M96 ACTIVE SOIC D 14 2500 Green (RoHS &

CD74HC86M96E4 ACTIVE SOIC D 14 2500 Green (RoHS &

CD74HC86M96G4 ACTIVE SOIC D 14 2500 Green (RoHS &

CD74HC86ME4 ACTIVE SOIC D 14 50 Green (RoHS &

CD74HC86MG4 ACTIVE SOIC D 14 50 Green(RoHS &

CD74HC86MT ACTIVE SOIC D 14 250 Green (RoHS &

CD74HC86MTE4 ACTIVE SOIC D 14 250 Green (RoHS &

CD74HC86MTG4 ACTIVE SOIC D 14 250 Green (RoHS &

CD74HCT86E ACTIVE PDIP N 14 25 Pb-Free

CD74HCT86EE4 ACTIVE PDIP N 14 25 Pb-Free

CD74HCT86M ACTIVE SOIC D 14 50 Green(RoHS &

CD74HCT86M96 ACTIVE SOIC D 14 2500 Green (RoHS &

CD74HCT86M96E4 ACTIVE SOIC D 14 2500 Green (RoHS &

CD74HCT86M96G4 ACTIVE SOIC D 14 2500 Green (RoHS &

CD74HCT86ME4 ACTIVE SOIC D 14 50 Green (RoHS &

CD74HCT86MG4 ACTIVE SOIC D 14 50 Green (RoHS &

CD74HCT86MT ACTIVE SOIC D 14 250 Green (RoHS &

CD74HCT86MTE4 ACTIVE SOIC D 14 250 Green (RoHS &

CD74HCT86MTG4 ACTIVE SOIC D 14 250 Green (RoHS &

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU N / A for Pkg Type

CU NIPDAU N / A for Pkg Type

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU N / A for Pkg Type

CU NIPDAU N / A for Pkg Type

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

9-Oct-2007

(3)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

(1)

The marketing status values are defined as follows:

9-Oct-2007

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

TAPE AND REEL INFORMATION

11-Mar-2008

*All dimensions are nominal

Device Package

Type

CD74HC86M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

CD74HCT86M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

Package
Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

CD74HC86M96 SOIC D 14 2500 346.0 346.0 33.0

CD74HCT86M96 SOIC D 14 2500 346.0 346.0 33.0

Pack Materials-Page 2

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