Texas Instruments CD74HCT75E, CD74HC75E, CD74HC75PWR, CD74HC75M96, CD74HC75M Datasheet
...
CD74HC75,
/
j
[ /Title
(CD74
HC75,
CD74
HCT75
)
Sub-
ect
(Dual
2-Bit
Bistabl
e
Data sheet acquired from Harris Semiconductor
SCHS135
March 1998
Features
• True and Complementary Outputs
• Buffered Inputs and Outputs
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
= 30%, NIH = 30% of V
IL
o
Pinout
C to 125oC
CC
CD74HCT75
Dual 2-Bit Bistable
Transparent Latch
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), VIH = 2V (Min)
IL
- CMOS Input Compatibility, I
Description
The Harris CD74HC75 and CD74HCT75 are dual 2-bit
bistable transparent latches. Each one of the 2-bit latches is
controlled by separate Enable inputs (
active LOW. When the Enable input is HIGH data enters the
latch and appears at the Q output. When the Enable input
(
1E and 2E) is LOW the output is not affected.
Ordering Information
≤ 1µA at VOL, V
l
1E and 2E) which are
OH
CD74HC75, CD74HCT75
(PDIP, SOIC)
TOP VIEW
1
1Q0
2
1D0
3
1D1
4
2E
5
V
CC
6
2D0
2D1
7
8
2Q1
1Q0
16
15
1Q1
14
1Q1
13
1E
12
GND
11
2Q0
10
2Q0
9
2Q1
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1998
1
File Number 1666.1
CD74HC75, CD74HCT75
Functional Diagram
16 (10)
2 (6)
D0
3 (7)
D1
E
1 OF 2
LATCHES
13 (4)
TRUTH TABLE
INPUTS OUTPUTS
D EQQ
LHLH
HHHL
XLQ0Q0
NOTE:
H = High Level
L = Low Level
X = Don’t Care
Q0 = The level of Q before the transition of E.
1 (11)
14 (8)
15 (9)
Q0
Q0
Q1
Q1
D0
E
D1
2 (6)
13 (4)
3 (7)
5
12
V
CC
GND
LATCH 0
QD
LE LE
LE LE
QD
LATCH 1
16 (10)
1 (11)
14 (8)
15 (9)
Q0
Q0
Q1
Q1
LE
Q
P
N
LE Q
FIGURE 1. LOGIC DIAGRAM FIGURE 2. LATCH DETAIL
LE
P
N
LE
2
CD74HC75, CD74HCT75
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, I
O
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Diode Current, I
OK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, I
O
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, V
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
CC
Thermal Resistance (Typical, Note 3) θJA (oC/W)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Maximum Junction Temperature (Hermetic P ac kage or Die) . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CC
DC Electrical Specifications
PARAMETER SYMBOL
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
V
IH
V
IL
V
OH
V
OL
I
I
TEST
CONDITIONS
25oC -40oC TO 85oC -55oC TO 125oC
VCC (V)
- - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
- - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
VIH or
V
-0.02 2 1.9 - - 1.9 - 1.9 - V
IL
4.5 4.4 - - 4.4 - 4.4 - V
6 5.9 - - 5.9 - 5.9 - V
---------V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
VIH or
V
0.02 2 - - 0.1 - 0.1 - 0.1 V
IL
4.5 - - 0.1 - 0.1 - 0.1 V
6 - - 0.1 - 0.1 - 0.1 V
---------V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
VCC or
-6--±0.1 - ±1-±1 µA
GND
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
3
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