Texas Instruments CD74HCT73M, CD74HCT73E, CD74HC73M96, CD74HC73M, CD74HC73E Datasheet

CD74HC73,

/
j

[ /Title
(CD74
HC73,
CD74
HCT73
)

Sub-

ect
(Dual
J-K
Flip­Flop

Data sheet acquired from Harris Semiconductor
SCHS134

February 1998

Features

• Hysteresis on Clock Inputs for Improved Noise
Immunity and Increased Input Rise and Fall Times

• Asynchronous Reset

• Complementary Outputs

• Buffered Inputs

• Typical f
T

= 25oC

A

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), VIH = 2V (Min)

V

IL

- CMOS Input Compatibility, I

= 60MHz at VCC = 5V, CL = 15pF,

MAX

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

o

C to 125oC

CC

OH

CD74HCT73

Dual J-K Flip-Flop with Reset

Negative-Edge Trigger

Description

The Harris CD74HC73 and CD74HCT73 utilize silicon gate
CMOS technology to achieve operating speeds equivalent to
LSTTL parts. They exhibit the low power consumption of
standard CMOS integrated circuits, together with the ability
to drive 10 LSTTL loads.

These flip-flops have independent J, K, Reset and Clock
inputs and Q and
negative-going transition of the clock pulse. Reset is
accomplished asynchronously by a low level input. This
device is functionally identical to the HC/HCT107 but differs
in terminal assignment and in some parametric limits.

The 74HCT logic family is functionally as well as pin
compatible with the standard 74LS logic family.

Ordering Information

PART NUMBER

CD74HC73E -55 to 125 14 Ld PDIP E14.3
CD74HCT73E -55 to 125 14 Ld PDIP E14.3
CD74HC73M -55 to 125 14 Ld SOIC M14.15

NOTES:

6. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

7. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.

Q outputs. They change state on the

TEMP. RANGE

(oC) PACKAGE

PKG.

NO.

Pinout

CD74HC73, CD74HCT73

(PDIP, SOIC)

TOP VIEW

1CP

1

1R

2
3

1K

V

4

CC

2CP

5

2R

6

2J

7

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

14

1J
1Q

13
12

1Q
GND

11

2K

10

2Q

9

2Q

8

1

File Number 1721.1

Functional Diagram

CD74HC73, CD74HCT73

R CP J K Q Q

LXXXLH

H
H

H
H
H H X X No Change

NOTE:
H =High Level (Steady State)
L =Low Level (Steady State)
X = Irrelevant

↓

= High-to-Low Transition

1K

1CP

1

2K

2CP

2R

14

1J

3

1

2

R

7

2J

10

5

6

FF 1

FF 2

12

1Q

13

Q

1

9

2Q

8

2

Q

GND = 11

= 4

V

CC

TRUTH TABLE

INPUTS OUTPUTS

↓
↓
↓
↓

L L No Change

HLHL

LHLH

H H Toggle

Logic Diagram

CP

14 (7)

J

3(10)

K

1 (5)

nA

2 (6)

R

J
K
CL
CL

R

12 (9)

Q

13 (8)

Q

2

CD74HC73, CD74HCT73

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

8. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Maximum Junction Temperature (Hermetic P ac kage or Die) . . . 175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

V

IH

V

IL

V

OH

V

OL

I

I

TEST

CONDITIONS

25oC -40oC TO 85oC -55oC TO 125oC

VCC (V)

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

---------V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIH or

V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

---------V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

3