TEXAS INSTRUMENTS CD54HC7266 Technical data

Data sheet acquired from Harris Semiconductor

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SCHS219D

August 1997 - Revised September 2003

CD54HC7266, CD74HC7266

High-Speed CMOS Logic

Quad 2-Input EXCLUSIVE NOR Gate

/Title
CD74H

7266)
Subject
High

peed

MOS

ogic

uad 2-

nput

XCLU­IVE

Features

• Four Independent EXCLUSIVE NOR Gates

• Buffered Inputs and Outputs

• Logical Comparators

• Parity Generators and Checkers

• Adders/Subtracters

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

o

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High NoiseImmunity: N

V

= 5V

CC

= 30%, NIH= 30%of VCCat

IL

C to 125oC

Description

The ’HC7266 contains four independent Exclusive NOR
gates in one package. They provide the system designer
with a means for implementation of the EXCLUSIVE NOR
function.

This device is functionally the same as the TTL226. They
differ in that the ’HC7266 has active high and low outputs
whereas the 226 has open collector outputs.

Ordering Information

TEMP. RANGE

PART NUMBER

CD54HC7266F3A -55 to 125 14 Ld CERDIP
CD74HC7266E -55 to 125 14 Ld PDIP
CD74HC7266M -55 to 125 14 Ld SOIC
CD74HC7266MT -55 to 125 14 Ld SOIC
CD74HC7266M96 -55 to 125 14 Ld SOIC

NOTE: When ordering,use the entire partnumber.The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.

(oC) PACKAGE

Pinout

1A
1B

1Y

2Y
2A
2B

GND

CD54HC7266

(CERDIP)

CD74HC7266

(PDIP, SOIC)

TOP VIEW

1
2
3
4
5
6
7

14

V

CC

4B

13
12

4A

11

4Y

10

3Y

9

3B

8

3A

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© 2003, Texas Instruments Incorporated

1

Functional Diagram

CD54HC7266, CD74HC7266

1

1A

2

1B

5

2A

6

2B

8

3A

9

3B

12

4A

13

4B

TRUTH TABLE

INPUTS OUTPUT

nA nB nY

LLH

3

4

10

11

GND = 7
V

CC

1Y

2Y

3Y

4Y

= 14

Logic Symbol

LHL
HLL
HHH

H = High Voltage Level, L = Low Voltage Level

nA

nY

nB

2

CD54HC7266, CD74HC7266

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

IK

OK

CC orIGND

O

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

CC

Thermal Resistance (Typical, Note 1) θJA (oC/W)

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 80

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 86

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

V

IH

V

IL

V

OH

V

OL

TEST

CONDITIONS

- - 2 1.5 - - 1.5 - 1.5 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

V

CC

(V)

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

Low Level Output
Voltage
TTL Loads

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

3

CD54HC7266, CD74HC7266

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

V

25oC -40oC TO 85oC -55oC TO 125oC

CC

(V)

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

Input Leakage

I

VCC or

I

Current
Quiescent Device

I

CC

VCC or

Current

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay t

Propagation Delay Time, Any
Input

Output Transition Times
(Figure 1)

Input Capacitance C
Power Dissipation

Capacitance

PLH,tPHLCL

t

PLH,tPHLCL

t

, t

TLH

IN

C

PD

(Note 2)

-6--±0.1 - ±1-±1 µA

GND

0 6 - - 2 - 20 - 40 µA

GND

, tf = 6ns

r

TEST

CONDITIONS V

CC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

= 50pF 2 - 115 145 150 ns

4.5 - 23 29 35 ns
6 - 30 25 30 ns

= 15pF 5 9 - - - ns

THLCL

= 50pF 2 - 75 95 110 ns

4.5 - 15 19 22 ns
6 - 13 16 19 ns

---1010 10pF

CL= 15pF 5 33 - - - pF

UNITSTYP MAX MAX MAX

NOTE:

2. CPDis used to determine the dynamic power consumption per gate, PD=V
Load Capacitance, VCC = Supply Voltage.

Test Circuit and Waveform

tr = 6ns tf = 6ns

t

PHL

90%
50%
10%

t

PLH

INPUT

t

THL

INVERTING

OUTPUT

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC

2

fi(CPD+CL) where fi= Input Frequency, CL= Output

CC

V

CC

GND

t

TLH

90%

50%

10%

4