Texas Instruments CD74HCT670M96, CD74HCT670M, CD74HCT670E, CD74HC670M96, CD74HC670M Datasheet

CD74HC670,

/

[ /Title
(CD74H
C670,
CD74H
CT670)

Subject
(High­Speed
CMOS
Logic
4x4 Reg­ister

Data sheet acquired from Harris Semiconductor
SCHS195

January 1998

Features

• Simultaneous and Independent Read and Write
Operations

• Expandable to 512 Words of n-Bits

• Three-State Outputs

• Organized as 4 Words x 4 Bits Wide

• Buffered Inputs

• Typical Read Time = 16ns for CD74HC670 V
= 15pF, TA = 25oC

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, NIH = 30% of V

IL

o

=5V,C

CC

C to 125oC

CC

CD74HCT670

High-Speed CMOS Logic

4x4 Register File

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,
V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

Description

The Harris CD74HC670 and CD74HCT670 are 16-bit register

L

files organized as 4 words x 4 bits each. Read and write
address and enableinputs allow simultaneous writing into one
location while reading another. Four data inputs are provided
to store the 4-bit word. The write address inputs (WA0 and
WA1)determine the location of the stored word in the register.
When write enable (
address location and it remains transparent to the data. The
outputs will reflect the true form of the input data. When (
is high data and address inputs are inhibited. Data acquisition
from the four registers is made possible by the read address
inputs (RA1 and RA0). The addressed word appears at the
output when the read enable (
high impedance state when the (
tied together to increase the word capacity to 512 x 4 bits.

WE) is low the word is entered into the

Ordering Information

≤ 1µA at VOL, V

l

RE) is low. The output is in the

RE) is high. Outputs can be

OH

WE)

Pinout

CD74HC670, CD74HCT670

(PDIP, SOIC)

TOP VIEW

D1
D2

D3
RA1
RA0

Q3

Q2

GND

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

V

CC

D0
WA0
WA1
WE
RE
Q0
Q1

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

1

File Number 1660.1

Functional Diagram

CD74HC670, CD74HCT670CD74HC670, CD74HCT670

15

D0

1

D1

2

D2

3

D3

12

WE

11

RE

RA1

RA0
WA0
WA1

4

WRITE MODE SELECT TABLE

INPUTS INTERNAL

OPERATING

MODE

N

LATCHES

(NOTE 3)WE D

Write Data L L L

LHH

Data Latched H X No Change

NOTE:

3. The WriteAddress (WA0 andWA1) to the“internal latches”must
be stable while WE is LOW for conventional operation.

10

Q0

9

Q1

7

Q2

6

Q3

514 13

READ MODE SELECT TABLE

INPUTS

INTERNAL

OPERATING

MODE

RE

LATCHES

(NOTE 4)

Read L L L

LHH

Disabled H X (Z)

NOTE:

4. The selectionof the “internal latches” byRead Address(RA0 and
RA1) are not constrained by WE or RE operation.
H = High Voltage Level
L = Low Voltage Level
X= Don’t Care
Z = High Impedance “Off” State

OUTPUT

Q

N

2

CD74HC670, CD74HCT670CD74HC670, CD74HCT670

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

5. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 5) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

V

IH

V

IL

V

OH

V

OL

I

I

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

CC

(V)

o

C -40oC TO 85oC -55oCTO125oC

25

UNITSV

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - - V

-6 4.5 3.98 - - 3.84 - 3.7 - V

-7.8 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - - V

6 4.5 - - 0.26 - 0.33 - 0.4 V

7.8 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1µA

GND

3