Texas Instruments CD74HCT597M96, CD74HCT597M, CD74HCT597E, CD74HC597M96, CD74HC597M Datasheet
...
CD74HC597,
/
j
[ /Title
(CD74
HC597
,
CD74
HCT59
7)
Subect
(High
Speed
CMOS
Data sheet acquired from Harris Semiconductor
SCHS191
January 1998
Features
• Buffered Inputs
• Asynchronous Parallel Load
• Typical f
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), VIH = 2V (Min)
IL
- CMOS Input Compatibility, I
= 60MHz at VCC=5V,CL= 15pF, TA=25oC
MAX
o
= 30%, NIH = 30% of V
IL
≤ 1µA at VOL, V
l
C to 125oC
CC
OH
CD74HCT597
High Speed CMOS Logic
8-Bit Shift Register with Input Storage
Description
The Harris CD74HC597 and CD74HCT597 are high-speed
silicon gate CMOS devices that are pin-compatible with the
LSTTL 597 devices. Each device consists of an 8-flip-flop
input register and an 8-bit parallel-in/serial-in, serial-out shift
register.Each register is controlled by its own clock. A “low”on
the parallel load input (
chronously into the shift register. A “low” master input (
clears the shift register. Serial input data can also be synchronously shifted through the shift register when
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE
CD74HC597E -55 to 125 16 Ld PDIP E16.3
CD74HCT597E -55 to 125 16 Ld PDIP E16.3
CD74HC597M -55 to 125 16 Ld SOIC M16.15
CD74HCT597M -55 to 125 16 Ld SOIC M16.15
NOTES:
1. When ordering, use the entire part number.Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.
PL) shifts parallel stored data asyn-
MR)
PL is high.
PKG.
NO.
Pinout
CD74HC597, CD74HCT597
(PDIP, SOIC)
TOP VIEW
V
1
D1
D2
2
D3
3
D4
4
5
D5
D6
6
7
D7
GND
8
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1998
1
16
CC
15
D0
14
D
S
13
PL
12
ST
CP
11
SH
CP
10
MR
9
Q7
File Number 1915.1
Functional Diagram
CD74HC597, CD74HCT597
PARALLEL
DAT A
INPUTS
ST
SH
DS
D0
D1
D2
D3
D4
D5
D6
D7
CP
CP
PL
MR
15
1
2
3
4
STORAGE
5
6
7
12
11
13
10
8 F/F
REG.
8-BIT
SHIFT
REG.
14
9
Q7
FUNCTION TABLE
ST
CP
SH
CP
PL MR FUNCTION
↑ X X X Data Loaded to Input Flip-Flops
↑ X L H Data Loaded from Inputs to Shift Register
No Clock Edge X L H Data Transferred from Input Flip-Flops to Shift Register
X X L L InvalidLogic, State of Shift Register Indeterminate when
Signals Removed
X X H L Shift Register Cleared
X ↑ H H Shift Register Clocked Qn = Qn-1, Q0 = D
S
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,↑ = Transition from Low to High CP Level
2
CD74HC597, CD74HCT597
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, I
O
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Source or Sink Current per Output Pin, I
O
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, V
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
CC
Thermal Resistance (Typical, Note 3) θJA (oC/W)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CC
DC Electrical Specifications
PARAMETER SYMBOL
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
V
IH
V
IL
V
OH
V
OL
I
I
TEST
CONDITIONS
V
CC
(V)
25oC -40oC TO 85oC -55oCTO125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
- - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
- - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
- - ---- - - -V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
- - ---- - - -V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
VCC or
-6--±0.1 - ±1-±1µA
GND
3
Loading...