TEXAS INSTRUMENTS CD54HC540F3A, CD54HC541F3A, CD54HCT541F3A, CD74HC540E, CD74HC540M Technical data

Data sheet acquired from Harris Semiconductor
SCHS189C

January 1998 - Revised July 2004

CD54/74HC540, CD74HCT540,

CD54/74HC541, CD54/74HCT541

High-Speed CMOS Logic

Octal Buffer and Line Drivers, Three-State

[ /Title
(CD74
HC540
,

D74

C
HCT54
0,
CD74
HC541
,

D74

C
HCT54

Features

• ’HC540, CD74HCT540 . . . . . . . . . . . . . . . . . . . Inverting

• ’HC541, ’HCT541. . . . . . . . . . . . . . . . . . . . . . Non-Inverting

• Buffered Inputs

• Three-State Outputs

• Bus Line Driving Capability

• Typical Propagation Delay = 9ns at V
C

= 15pF, TA = 25oC

L

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

CC

= 5V,

o

C to 125oC

CC

OH

Description

The ’HC540 and CD74HCT540 are Inverting Octal Buffers
and Line Drivers with Three-State Outputs and the capability
to drive 15 LSTTL loads. The ’HC541 and ’HCT541 are Non­Inverting Octal Buffersand Line Drivers with Three-State Out­puts that can driv e 15 LSTTL loads. The Output Enables
(

OE1) and (OE2) control the Three-State Outputs. If either
OE1 or OE2 is HIGH the outputs will be in the high imped­ance state. For data output

OE1 and OE2 both must be LOW.

Ordering Information

TEMP. RANGE

PART NUMBER

CD54HC540F3A -55 to 125 20 Ld CERDIP

CD54HC541F3A -55 to 125 20 Ld CERDIP

CD54HCT541F3A -55 to 125 20 Ld CERDIP

CD74HC540E -55 to 125 20 Ld PDIP

CD74HC540M -55 to 125 20 Ld SOIC

CD74HC540M96 -55 to 125 20 Ld SOIC

CD74HC541E -55 to 125 20 Ld PDIP

CD74HC541M -55 to 125 20 Ld SOIC

CD74HC541M96 -55 to 125 20 Ld SOIC

CD74HC541PW -55 to 125 20 Ld TSSOP

CD74HC541PWR -55 to 125 20 Ld TSSOP

CD74HCT540E -55 to 125 20 Ld PDIP

CD74HCT540M -55 to 125 20 Ld SOIC

CD74HCT540M96 -55 to 125 20 Ld SOIC

CD74HCT541E -55 to 125 20 Ld PDIP

CD74HCT541M -55 to 125 20 Ld SOIC

CD74HCT541M96 -55 to 125 20 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96

denotes tape and reel.

(oC) PACKAGE

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© 2004, Texas Instruments Incorporated

1

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

Pinouts

CD54HC540

(CERDIP)

CD74HC540, CD74HCT540

(PDIP, SOIC)

TOP VIEW

1

OE

A0

2

A1

3

A2

4

A3

5

A4

6

A5

7
8

A6

9

A7

GND

10

Functional Diagram

CD54HC541, CD54HCT541

(CERDIP)

CD74HC541

(PDIP, SOIC, TSSOP)

CD74HCT541

OE1

A0
A1
A2
A3
A4
A5
A6
A7

(PDIP, SOIC)

TOP VIEW

1
2
3
4
5
6
7
8
9

10

V

20

CC

OE2

19

Y0

18

Y1

17

Y2

16

Y3

15

Y4

14

Y5

13
12

Y6
Y7

11

V

20

CC

OE2

19

Y0

18

Y1

17

Y2

16

Y3

15

Y4

14

Y5

13
12

Y6

11

Y7

GND

OE

A

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

OE

B

540 541

Y

Y

0

Y

Y

1

Y

Y

2

Y

Y

3

Y

Y

4

Y

Y

5

Y

Y

6

Y

Y

7

0

1

2

3

4

5

6

7

2

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

TRUTH TABLE

INPUTS OUTPUTS

OE1 OE2 An 540 541

LLHLH
HXXZZ
XHXZZ

LLLHL

H = HIGH Voltage Level
L = LOW Voltage Level
X= Don’t Care
Z = High Impedance

3

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

CC

Thermal Resistance (Typical, Note 1) θJA (oC/W)

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

V

IH

V

IL

V

OH

V

OL

I

I

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

CC

(V)

o

C -40oC TO 85oC -55oC TO 125oC

25

UNITSV

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - - V

-6 4.5 3.98 - - 3.84 - 3.7 - V

-7.8 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - - V
6 4.5 - - 0.26 - 0.33 - 0.4 V

7.8 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

4

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Quiescent Device

I

CC

Current
Three-State Leakage

I

OZ

Current

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

V

IL

V

OH

CMOS Loads
High Level Output

Voltage
TTL Loads

Low Level Output

V

OL

Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Three-State Leakage

I

I

I

CC

OZ

I

Current

Additional Quiescent
Device Current Per

∆I

CC

(Note 2)

Input Pin: 1 Unit Load

NOTE:

2. For dual-supply systems theoretical worst case (V

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

VCC or

GND

VILor VIHVO =

VCC or

GND

- - 4.5 to

- - 4.5 to

VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V

VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V

VCCand

GND

VCC or

GND

VILor VIHVO =

VCC or

GND

V

CC

-2.1

o

C -40oC TO 85oC -55oC TO 125oC

V

CC

(V)

25

UNITSV

0 6 - - 8 - 80 - 160 µA

6--±0.5 - ±5.0 - ±10 µA

2--2 - 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

-6 4.5 3.98 - - 3.84 - 3.7 - V

6 4.5 - - 0.26 - 0.33 - 0.4 V

0 5.5 - ±0.1 - ±1-±1 µA

0 5.5 - - 8 - 80 - 160 µA

5.5 - - ±0.5 - ±5.0 - ±10 µA

- 4.5 to

- 100 360 - 450 - 490 µA

5.5

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

HCT Input Loading Table

UNIT LOADS

INPUT

A0 - A7 1 0.4

OE2 0.75 0.75
OE1 1.15 1.15

NOTE: Unit Load is ∆ICClimitspecificinDCElectricalSpecifications
Table, e.g., 360µA max. at 25oC.

HCT540 HCT541

5