TEXAS INSTRUMENTS CD54HC540F3A, CD54HC541F3A, CD54HCT541F3A, CD74HC540E, CD74HC540M Technical data

Data sheet acquired from Harris Semiconductor
SCHS189C

January 1998 - Revised July 2004

CD54/74HC540, CD74HCT540,

CD54/74HC541, CD54/74HCT541

High-Speed CMOS Logic

Octal Buffer and Line Drivers, Three-State

[ /Title
(CD74
HC540
,

D74

C
HCT54
0,
CD74
HC541
,

D74

C
HCT54

Features

• ’HC540, CD74HCT540 . . . . . . . . . . . . . . . . . . . Inverting

• ’HC541, ’HCT541. . . . . . . . . . . . . . . . . . . . . . Non-Inverting

• Buffered Inputs

• Three-State Outputs

• Bus Line Driving Capability

• Typical Propagation Delay = 9ns at V
C

= 15pF, TA = 25oC

L

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

CC

= 5V,

o

C to 125oC

CC

OH

Description

The ’HC540 and CD74HCT540 are Inverting Octal Buffers
and Line Drivers with Three-State Outputs and the capability
to drive 15 LSTTL loads. The ’HC541 and ’HCT541 are Non­Inverting Octal Buffersand Line Drivers with Three-State Out­puts that can driv e 15 LSTTL loads. The Output Enables
(

OE1) and (OE2) control the Three-State Outputs. If either
OE1 or OE2 is HIGH the outputs will be in the high imped­ance state. For data output

OE1 and OE2 both must be LOW.

Ordering Information

TEMP. RANGE

PART NUMBER

CD54HC540F3A -55 to 125 20 Ld CERDIP

CD54HC541F3A -55 to 125 20 Ld CERDIP

CD54HCT541F3A -55 to 125 20 Ld CERDIP

CD74HC540E -55 to 125 20 Ld PDIP

CD74HC540M -55 to 125 20 Ld SOIC

CD74HC540M96 -55 to 125 20 Ld SOIC

CD74HC541E -55 to 125 20 Ld PDIP

CD74HC541M -55 to 125 20 Ld SOIC

CD74HC541M96 -55 to 125 20 Ld SOIC

CD74HC541PW -55 to 125 20 Ld TSSOP

CD74HC541PWR -55 to 125 20 Ld TSSOP

CD74HCT540E -55 to 125 20 Ld PDIP

CD74HCT540M -55 to 125 20 Ld SOIC

CD74HCT540M96 -55 to 125 20 Ld SOIC

CD74HCT541E -55 to 125 20 Ld PDIP

CD74HCT541M -55 to 125 20 Ld SOIC

CD74HCT541M96 -55 to 125 20 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96

denotes tape and reel.

(oC) PACKAGE

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© 2004, Texas Instruments Incorporated

1

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

Pinouts

CD54HC540

(CERDIP)

CD74HC540, CD74HCT540

(PDIP, SOIC)

TOP VIEW

1

OE

A0

2

A1

3

A2

4

A3

5

A4

6

A5

7
8

A6

9

A7

GND

10

Functional Diagram

CD54HC541, CD54HCT541

(CERDIP)

CD74HC541

(PDIP, SOIC, TSSOP)

CD74HCT541

OE1

A0
A1
A2
A3
A4
A5
A6
A7

(PDIP, SOIC)

TOP VIEW

1
2
3
4
5
6
7
8
9

10

V

20

CC

OE2

19

Y0

18

Y1

17

Y2

16

Y3

15

Y4

14

Y5

13
12

Y6
Y7

11

V

20

CC

OE2

19

Y0

18

Y1

17

Y2

16

Y3

15

Y4

14

Y5

13
12

Y6

11

Y7

GND

OE

A

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

OE

B

540 541

Y

Y

0

Y

Y

1

Y

Y

2

Y

Y

3

Y

Y

4

Y

Y

5

Y

Y

6

Y

Y

7

0

1

2

3

4

5

6

7

2

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

TRUTH TABLE

INPUTS OUTPUTS

OE1 OE2 An 540 541

LLHLH
HXXZZ
XHXZZ

LLLHL

H = HIGH Voltage Level
L = LOW Voltage Level
X= Don’t Care
Z = High Impedance

3

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

CC

Thermal Resistance (Typical, Note 1) θJA (oC/W)

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

V

IH

V

IL

V

OH

V

OL

I

I

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

CC

(V)

o

C -40oC TO 85oC -55oC TO 125oC

25

UNITSV

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - - V

-6 4.5 3.98 - - 3.84 - 3.7 - V

-7.8 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - - V
6 4.5 - - 0.26 - 0.33 - 0.4 V

7.8 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

4

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Quiescent Device

I

CC

Current
Three-State Leakage

I

OZ

Current

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

V

IL

V

OH

CMOS Loads
High Level Output

Voltage
TTL Loads

Low Level Output

V

OL

Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Three-State Leakage

I

I

I

CC

OZ

I

Current

Additional Quiescent
Device Current Per

∆I

CC

(Note 2)

Input Pin: 1 Unit Load

NOTE:

2. For dual-supply systems theoretical worst case (V

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

VCC or

GND

VILor VIHVO =

VCC or

GND

- - 4.5 to

- - 4.5 to

VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V

VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V

VCCand

GND

VCC or

GND

VILor VIHVO =

VCC or

GND

V

CC

-2.1

o

C -40oC TO 85oC -55oC TO 125oC

V

CC

(V)

25

UNITSV

0 6 - - 8 - 80 - 160 µA

6--±0.5 - ±5.0 - ±10 µA

2--2 - 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

-6 4.5 3.98 - - 3.84 - 3.7 - V

6 4.5 - - 0.26 - 0.33 - 0.4 V

0 5.5 - ±0.1 - ±1-±1 µA

0 5.5 - - 8 - 80 - 160 µA

5.5 - - ±0.5 - ±5.0 - ±10 µA

- 4.5 to

- 100 360 - 450 - 490 µA

5.5

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

HCT Input Loading Table

UNIT LOADS

INPUT

A0 - A7 1 0.4

OE2 0.75 0.75
OE1 1.15 1.15

NOTE: Unit Load is ∆ICClimitspecificinDCElectricalSpecifications
Table, e.g., 360µA max. at 25oC.

HCT540 HCT541

5

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

Switching Specifications C

PARAMETER SYMBOL

= 50pF, Input tr, tf= 6ns

L

TEST

CONDITIONS V

CC

(V)

25oC

-40oC TO
85oC

-55oC TO
125oC

HC TYPES

Propagation Delay t

PLH

, t

PHLCL

= 50pF

Data to Outputs (540) 2 - - 110 - 140 - 165 ns

4.5 - - 22 - 28 - 33 ns
CL = 15pF 5 - 9 - - - - - ns
CL = 50pF 6 - - 19 - 24 - 28 ns

Data to Outputs (541) t

PLZ,tPHZ

CL = 50pF 2 - - 115 - 145 - 175 ns

4.5 - - 23 - 29 - 35 ns
CL = 15pF 5 - 9 - - - - - ns
CL = 50pF 6 - - 20 - 25 - 30 ns

Output Enable and Disable
to Outputs (540)

t

PLZ,tPHZ

CL = 50pF 2 - - 160 - 200 - 240 ns

4.5 - - 32 - 40 - 48 ns
CL = 15pF 5 - 13 - - - - - ns
CL = 50pF 6 - - 27 - 34 - 41 ns

Output Enable and Disable
to Outputs (541)

t

PLZ,tPHZ

CL = 50pF 2 - - 160 - 200 - 240 ns

4.5 - - 32 - 40 - 48 ns
CL = 15pF 5 - 14 - - - - - ns
CL = 50pF 6 - - 23 - 29 - 35 ns

Output Transition Time t

THL

, t

TLHCL

= 50pF 2 - - 60 - 75 - 90 ns

4.5 - - 12 - 15 - 18 ns

6 - - 10 - 13 - 15 ns
Input Capacitance C
Three-State Output

I

C

O

CL = 50pF - 10 - 10 - 10 - 10 pF

- - 20 - 20 - 20 - 20 pF

Capacitance
Power Dissipation Capacitance

C

PD

CL = 15pF 5 - 50 - - - - - pF

(Notes 3, 4) (540)
Power Dissipation Capacitance

C

PD

CL = 15pF 5 - 48 - - - - - pF

(Notes 3, 4) (541)

HCT TYPES

Propagation Delay t

PHL,tPLH

Data to Outputs (540) CL = 50pF 4.5 - - 24 - 30 - 36 ns

CL = 15pF 5 - 9 - - - - - ns

Data to Outputs (541) t

PHL,tPLH

CL = 50pF 4.5 - - 28 - 35 - 42 ns
CL = 15pF 5 - 11 - - - - - ns

Output Enable and Disable
to Outputs (540, 541)

Output Transition Time t
Input Capacitance C

t

PLZ,tPHZ

, t

TLH

THLCL

I

CL = 50pF 4.5 - - 35 - 44 - 53 ns
CL = 15pF 5 - 14 - - - - - ns

= 50pF 4.5 - - 12 - 15 - 18 ns

CL = 50pF - 10 - 10 - 10 - 10 pF

UNITSMIN TYP MAX MIN MAX MIN MAX

6

D

O

D

O

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

Switching Specifications C

= 50pF, Input tr, tf= 6ns (Continued)

L

TEST

PARAMETER SYMBOL

Three-State Output

C

CONDITIONS VCC(V)

O

- - 20 - 20 - 20 - 20 pF

Capacitance
Power Dissipation Capacitance

C

PD

CL = 15pF 5 - 55 - - - - - pF

(Notes 3, 4) (540, 541)

NOTES:

3. CPD is used to determine the dynamic power consumption, per channel.

4. PD = V

2

fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

CC

Test Circuits and Waveforms

tr = 6ns tf = 6ns

V

t

CC

GND

TLH

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

90%
50%
10%

t

90%

50%

10%

PLH

25oC

tr = 6ns

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

-40oC TO
85oC

2.7V

1.3V

0.3V

t

PLH

-55oC TO
125oC

= 6ns

t

f

90%

1.3V

10%

t

UNITSMIN TYP MAX MIN MAX MIN MAX

3V

GND

TLH

FIGURE 1. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

6ns 6ns

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

UTPUT HIGH

TO OFF

50%

t

t

OUTPUTS
ENABLED

PLZ

PHZ

10%

90%

90%

10%

t

PZL

t

PZH

OUTPUTS

DISABLED

50%

50%

FIGURE 3. HCTHREE-STATE PROPAGATION DELAY

WAVEFORM

V

CC

GN

OUTPUTS
ENABLED

FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

t

r

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

UTPUT HIGH

TO OFF

t

t

OUTPUTS
ENABLED

6ns t

PLZ

PHZ

10%

90%

f

2.7

1.3

OUTPUTS

DISABLED

0.3

t

t

PZH

6ns

PZL

1.3V

1.3V
OUTPUTS

ENABLED

FIGURE 4. HCTTHREE-STATE PROPAGATION DELAY

WAVEFORM

3V

GN

7

Test Circuits and Waveforms (Continued)

T

H

NOTE: Open drain waveforms t
VCC, CL = 50pF.

FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

PLZ

OTHER

INPUTS

IED HIGH

OR LOW

OUTPUT

DISABLE

and t

PZL

IC WITH

THREE-

STATE

OUTPUT

OUTPUT
R

= 1kΩ

L

C

L

50pF

VCC FOR t
GND FOR t

PLZ

PHZ

AND t

AND t

PZL

PZ

are the same as those for three-state shown on the left. The test circuit is Output RL=1kΩ to

8

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

CD54HC540F3A ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC

CD54HC541F ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC

CD54HC541F3A ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC

CD54HCT541F ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC

CD54HCT541F3A ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC

CD74HC540E ACTIVE PDIP N 20 20 Pb-Free

CD74HC540EE4 ACTIVE PDIP N 20 20 Pb-Free

CD74HC540M ACTIVE SOIC DW 20 25 Green (RoHS &

CD74HC540M96 ACTIVE SOIC DW 20 2000 Green (RoHS &

CD74HC540M96E4 ACTIVE SOIC DW 20 2000 Green (RoHS &

CD74HC540ME4 ACTIVE SOIC DW 20 25 Green (RoHS &

CD74HC541E ACTIVE PDIP N 20 20 Pb-Free

CD74HC541EE4 ACTIVE PDIP N 20 20 Pb-Free

CD74HC541M ACTIVE SOIC DW 20 25 Green (RoHS &

CD74HC541M96 ACTIVE SOIC DW 20 2000 Green (RoHS &

CD74HC541M96E4 ACTIVE SOIC DW 20 2000 Green (RoHS &

CD74HC541PW ACTIVE TSSOP PW 20 70 Green (RoHS &

CD74HC541PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS &

CD74HC541PWR ACTIVE TSSOP PW 20 2000 Green (RoHS &

CD74HC541PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS &

CD74HC541SM OBSOLETE SSOP DB 20 Green (RoHS &

CD74HCT540E ACTIVE PDIP N 20 20 Pb-Free

CD74HCT540EE4 ACTIVE PDIP N 20 20 Pb-Free

CD74HCT540M ACTIVE SOIC DW 20 25 Green (RoHS &

CD74HCT540M96 ACTIVE SOIC DW 20 2000 Green (RoHS &

CD74HCT540M96E4 ACTIVE SOIC DW 20 2000 Green (RoHS &

CD74HCT541E ACTIVE PDIP N 20 20 Pb-Free

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-NC-NC-NC

CU NIPDAU Level-NC-NC-NC

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-NC-NC-NC

CU NIPDAU Level-NC-NC-NC

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-NC-NC-NC

CU NIPDAU Level-NC-NC-NC

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-NC-NC-NC

17-Oct-2005

(3)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

CD74HCT541EE4 ACTIVE PDIP N 20 20 Pb-Free

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-NC-NC-NC

17-Oct-2005

(3)

(RoHS)

CD74HCT541M ACTIVE SOIC DW 20 25 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD74HCT541M96 ACTIVE SOIC DW 20 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD74HCT541M96E4 ACTIVE SOIC DW 20 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD74HCT541ME4 ACTIVE SOIC DW 20 25 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,65

28

1

2,00 MAX

0,38
0,22

15

14

A

0,05 MIN

0,15

5,60
5,00

M

8,20
7,40

Seating Plane

0,10

0,25
0,09

0°–ā8°

Gage Plane

0,25

0,95
0,55

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

14

6,50

6,50

5,905,90

2016

7,50

6,90

24

8,50

28

10,50

9,907,90

30

10,50

9,90

38

12,90

12,30

4040065 /E 12/01

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

1,20 MAX

14

0,30
0,19

8

4,50
4,30

PINS **

7

Seating Plane

0,15
0,05

8

1

A

DIM

14

0,10

6,60
6,20

M

0,10

0,15 NOM

0°–8°

2016

Gage Plane

24

0,25

0,75
0,50

28

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

4040064/F 01/97

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty . Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:

Products Applications

Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive

DSP dsp.ti.com Broadband www.ti.com/broadband
Interface interface.ti.com Digital Control www.ti.com/digitalcontrol
Logic logic.ti.com Military www.ti.com/military
Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security

Telephony www.ti.com/telephony
Video & Imaging www.ti.com/video
Wireless www.ti.com/wireless

Mailing Address: Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

Copyright  2005, Texas Instruments Incorporated