Data sheet acquired from Harris Semiconductor
SCHS216
November 1997
CD74HC4518, CD74HC4520,
CD74HCT4520
High Speed CMOS Logic
Dual Synchronous Counters
[ /Title
(CD74
HC451
8,
CD74
HC452
0,
CD74
HCT45
20)
Subect
Features
• Positive or Negative Edge Triggering
• Synchronous Internal Carry Propagation
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
= 30%, NIH = 30% of V
IL
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), VIH = 2V (Min)
IL
- CMOS Input Compatibility, I
≤ 1µA at VOL, V
l
o
C to 125oC
OH
Description
The Harris CD74HC4518 is a dual BCD up-counter. The
Harris CD74HC4520 and CD74HCT4520 are dual binary
up-counters. Each device consists of two independent
internally synchronous 4-stage counters. The counter stages
are D-type flip-flops having interchangeable CLOCK and
ENABLE lines for incrementing on either the positive-going
or the negative-going transition of CLOCK. The counters are
cleared by high levels on the MASTER RESET lines. The
counter can be cascaded in the ripple mode by connecting
Q
to the ENABLE input of the subsequent counter while the
3
CLOCK input of the latter is held low.
Ordering Information
CC
PART NUMBER TEMP. RANGE (oC) PACKAGE
CD74HC4518E -55 to 125 16 Ld PDIP E16.3
CD74HC4520E -55 to 125 16 Ld PDIP E16.3
CD74HCT4520E -55 to 125 16 Ld PDIP E16.3
CD74HC4520M -55 to 125 16 Ld SOIC M16.15
CD74HCT4520M -55 to 125 16 Ld SOIC M16.15
PKG.
NO.
Pinout
NOTES:
1. When ordering, use the entire partnumber. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer or diefor this partnumber is availablewhich meets allelectrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
CD74HC4518
CD74HC4520, CD74HCT4520
(PDIP, SOIC)
TOP VIEW
V
1CP
1E
1Q
1Q
1Q
1Q
1MR
GND
1
2
3
0
4
1
5
2
6
3
7
8
16
2MR
15
14
2Q
13
2Q
12
2Q
11
2Q
10
2E
2CP
9
CC
3
2
1
0
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1997
1
File Number 1665.1
Functional Diagram
NOTE:
H = High State.
L = Low State.
↑ = High-to-Low Transition.
↓ = Low-to-High Transition.
X = Don’t Care.
CD74HC4518, CD74HC4520, CD74HCT4520
R
R
3
1Q
4
1Q
5
1Q
6
1Q
11
2Q
12
2Q
13
2Q
14
2Q
GND = 8
VCC = 16
0
1
2
3
0
1
2
3
thru Q3 = L
0
1CP
1E
1MR
2CP
2E
2MR
1
2
7
9
10
15
÷10/÷16
CL
÷10/÷16
CL
TRUTH TABLE
CP E MR OUTPUT STATE
↑ H L Increment Counter
L ↓ L Increment Counter
↓ X L No Change
X ↑ L No Change
↑ L L No Change
H ↓ L No Change
XXHQ
2
CD74HC4518, CD74HC4520, CD74HCT4520
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, I
O
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, V
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
CC
Thermal Resistance (Typical, Note 3) θJA (oC/W)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CC
DC Electrical Specifications
PARAMETER SYMBOL
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
V
IH
V
IL
V
OH
V
OL
I
I
I
CC
TEST
CONDITIONS
(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
I
VCC (V)
o
C -40oCTO85oC
25
-55oC TO
125oC
UNITSV
- - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
- - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
- - -------V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
- - -------V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
VCC or
-6--±0.1 - ±1-±1µA
GND
VCC or
0 6 - - 8 - 80 - 160 µA
GND
3