Texas Instruments CD74HCT42E, CD74HC42M, CD74HC42E, CD54HC42F3A Datasheet

CD74HC42,

/

[ /Title
(CD74H
C42,
CD74H
CT42)

Subject
(High
Speed
CMOS
Logic
BCD To
Deci-

Data sheet acquired from Harris Semiconductor
SCHS133

August 1997

Features

• Buffered Inputs and Outputs

• Typical Propagation Delay: 12ns at V
C

= 15pF, TA = 25oC

L

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

CC

= 5V,

o

C to 125oC

CC

OH

CD74HCT42

High Speed CMOS Logic

BCD To Decimal Decoder (1 of 10)

Description

The Harris CD74HC42, CH74HCT42 BCD-to-Decimal
Decoders utilize silicon-gate CMOS technology to achieve
operating speeds similar to LSTTL decoders with the low
power consumption of standard CMOS integrated circuits.
These devices have the capability of driving 10 LSTLL loads
and are compatible with the standard 74LS logic family. One
of ten outputs (low on select) is selected in accordance with
the BCD input. Non-valid BCD inputs result in none of the
outputs being selected (all outputs are high).

Ordering Information

PKG.

PART NUMBER TEMP. RANGE (oC) PACKAGE

CD74HC42E -55 to 125 16 Ld PDIP E16.3
CD74HCT42E -55 to 125 16 Ld PDIP E16.3
CD74HC42M -55 to 125 16 Ld SOIC M16.15

NOTES:

1. When ordering, use the entire partnumber. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Die for this part number is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.

NO.

Pinout

CD74HC42, CD74HCT42

(PDIP, SOIC)

TOP VIEW

16

1

Y0

2

Y1

3

Y2

4

Y3

5

Y4

6

Y5

7

Y6

8

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

1

V

CC

15

A0

14

A1

13

A2

12

A3

11

Y9

10

Y8

9

Y7

File Number 1689.1

CD74HC42, CD74HCT42

Functional Diagram

1

Y0

15

A0

14

A1

13

A2

12

A3

TRUTH TABLE

INPUTS OUTPUTS

A3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9

LLLLLHHHHHHHHH

2

Y1

3

Y2

4

Y3

5

Y4

6

Y5

7

Y6

9

Y7

10

Y8

11

Y9

LLLHHLHHHHHHHH
LLHLHHLHHHHHHH
LLHHHHHLHHHHHH
LHLLHHHHLHHHHH
LHLHHHHHHLHHHH
LHHLHHHHHHLHHH

LHHHHHHHHHHLHH
HLLLHHHHHHHHLH
HLLHHHHHHHHHHL
HLHLHHHHHHHHHH
HLHHHHHHHHHHHH
HHL LHHHHHHHHHH
HHLHHHHHHHHHHH
HHHLHHHHHHHHHH
HHHHHHHHHHHHHH

NOTE: H = High Voltage Level, L = Low Voltage Level

2