Texas Instruments CD74HCT42E, CD74HC42M, CD74HC42E, CD54HC42F3A Datasheet

CD74HC42,

/

[ /Title
(CD74H
C42,
CD74H
CT42)

Subject
(High
Speed
CMOS
Logic
BCD To
Deci-

Data sheet acquired from Harris Semiconductor
SCHS133

August 1997

Features

• Buffered Inputs and Outputs

• Typical Propagation Delay: 12ns at V
C

= 15pF, TA = 25oC

L

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

CC

= 5V,

o

C to 125oC

CC

OH

CD74HCT42

High Speed CMOS Logic

BCD To Decimal Decoder (1 of 10)

Description

The Harris CD74HC42, CH74HCT42 BCD-to-Decimal
Decoders utilize silicon-gate CMOS technology to achieve
operating speeds similar to LSTTL decoders with the low
power consumption of standard CMOS integrated circuits.
These devices have the capability of driving 10 LSTLL loads
and are compatible with the standard 74LS logic family. One
of ten outputs (low on select) is selected in accordance with
the BCD input. Non-valid BCD inputs result in none of the
outputs being selected (all outputs are high).

Ordering Information

PKG.

PART NUMBER TEMP. RANGE (oC) PACKAGE

CD74HC42E -55 to 125 16 Ld PDIP E16.3
CD74HCT42E -55 to 125 16 Ld PDIP E16.3
CD74HC42M -55 to 125 16 Ld SOIC M16.15

NOTES:

1. When ordering, use the entire partnumber. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Die for this part number is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.

NO.

Pinout

CD74HC42, CD74HCT42

(PDIP, SOIC)

TOP VIEW

16

1

Y0

2

Y1

3

Y2

4

Y3

5

Y4

6

Y5

7

Y6

8

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

1

V

CC

15

A0

14

A1

13

A2

12

A3

11

Y9

10

Y8

9

Y7

File Number 1689.1

CD74HC42, CD74HCT42

Functional Diagram

1

Y0

15

A0

14

A1

13

A2

12

A3

TRUTH TABLE

INPUTS OUTPUTS

A3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9

LLLLLHHHHHHHHH

2

Y1

3

Y2

4

Y3

5

Y4

6

Y5

7

Y6

9

Y7

10

Y8

11

Y9

LLLHHLHHHHHHHH
LLHLHHLHHHHHHH
LLHHHHHLHHHHHH
LHLLHHHHLHHHHH
LHLHHHHHHLHHHH
LHHLHHHHHHLHHH

LHHHHHHHHHHLHH
HLLLHHHHHHHHLH
HLLHHHHHHHHHHL
HLHLHHHHHHHHHH
HLHHHHHHHHHHHH
HHL LHHHHHHHHHH
HHLHHHHHHHHHHH
HHHLHHHHHHHHHH
HHHHHHHHHHHHHH

NOTE: H = High Voltage Level, L = Low Voltage Level

2

CD74HC42, CD74HCT42

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

V

IH

V

IL

V

OH

V

OL

I

I

I

CC

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

CC

(V)

o

25

C -40oC TO 85oC -55oC TO 125oC

UNITSV

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - -V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - -V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

VCC or

0 6 - - 8 - 80 - 160 µA

GND

3

CD74HC42, CD74HCT42

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

HCT TYPES

High Level Input
Voltage

Low Level Input

V

IH

V

IL

Voltage
High Level Output

Voltage

V

OH

CMOS Loads
High Level Output

Voltage
TTL Loads

Low Level Output

V

OL

Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Additional Quiescent

I

I

I

CC

∆I

CC

Device Current Per
Input Pin: 1 Unit Load

NOTE: For dual-supply systems theoretical worst case (V

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

- - 4.5 to

- - 4.5 to

VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V

4 4.5 - - 0.26 - 0.33 - 0.4 V

VCCand

0 5.5 - ±0.1 - ±1-±1 µA

GND

VCC or

0 5.5 - - 8 - 80 - 160 µA

GND

V

CC

- 4.5 to

-2.1

o

C -40oC TO 85oC -55oC TO 125oC

V

CC

25

(V)

2--2- 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

- 100 360 - 450 - 490 µA

5.5

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

UNITSV

HCT Input Loading Table

INPUT UNIT LOADS

All 1

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Table, e.g.
360µA max at 25oC.

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay,
Input to Y (Figure 1)

Any Input to Yt
Output Transition Time

(Figure 1)

Input Capacitance C

r

t

PLH,tPHL

, t

PLH

PHL

t

, t

TLH

THL

IN

, tf = 6ns

TEST

CONDITIONS VCC(V)

CL= 50pF 2 - - 150 - 190 - 225 ns

CL= 15pF 5 - 12 - - - - - ns
CL= 50pF 2 - - 75 - 95 - 110 ns

- - - - 10 - 10 - 10 pF

25oC

-40oC TO
85oC

-55oC TO
125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

4.5 - - 30 - 38 - 45 ns
6 - - 26 - 33 - 38 ns

4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns

4

CD74HC42, CD74HCT42

Switching Specifications Input t

, tf = 6ns (Continued)

r

TEST

PARAMETER SYMBOL

Power Dissipation Capacitance

C

CONDITIONS VCC(V)

PD

-5-65-----pF

(Notes 4, 5)

HCT TYPES

Propagation Delay,

t

PLH

, t

CL= 50pF 4.5 - - 35 - 44 - 53 ns

PHL

Input to Y (Figure 2)
Any Input to Yt
Output Transition Time

PLH

t

TLH

, t
, t

CL= 15pF 5 - 14 - - - - - ns

PHL

CL= 50pF 4.5 - - 15 - 19 - 22 ns

THL

(Figure 2)
Input Capacitance C
Power Dissipation Capacitance

IN

C

PD

- - - - 10 - 10 - 10 pF

-5-70-----pF

(Notes 4, 5)

NOTES:

4. CPD is used to determine the dynamic power consumption, per package.

5. PD = V

2

fi(CPD + CL) where: fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

CC

Test Circuits and Waveforms

tr = 6ns tf = 6ns

V

t

CC

GND

TLH

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

90%
50%
10%

t

90%

50%

10%

PLH

25oC

tr = 6ns

INPUT

t

INVERTING

OUTPUT

THL

-40oC TO

t

PHL

85oC

2.7V

1.3V

0.3V

t

PLH

-55oC TO
125oC

= 6ns

t

f

t

90%

1.3V

10%

UNITSMIN TYP MAX MIN MAX MIN MAX

3V

GND

TLH

FIGURE 4. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

FIGURE 5. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

5

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