Texas Instruments CD74HCT4075E, CD74HC4075PWR, CD74HC4075M96, CD74HC4075M, CD74HC4075E Datasheet

CD74HC4075,

/

[ /Title
(CD74H
C4075,
CD74H
CT4075)

Subject
(High
Speed
CMOS
Logic
Triple 3­Input

Data sheet acquired from Harris Semiconductor
SCHS210

August 1997

Features

• Buffered Inputs

• Typical Propagation Delay: 8ns at V
C

= 15pF, TA = 25oC

L

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

CC

= 5V,

o

C to 125oC

CC

OH

CD74HCT4075

High Speed CMOS Logic

Triple 3-Input OR Gate

Description

The Harris CD74HC4075, CD74HCT4075 logic gates utilize
silicon-gate CMOS technology to achieve operating speeds
similar to LSTTL gates with the low power consumption of
standard CMOS integrated circuits. All devices have the
ability to drive 10 LSTTL loads. The 74HCT logic family is
functionally pin compatible with the standard 74LS logic
family.

Ordering Information

PKG.

PART NUMBER TEMP. RANGE (oC) PACKAGE

CD74HC4075E -55 to 125 14 Ld PDIP E14.3
CD74HC4075E -55 to 125 14 Ld PDIP E14.3
CD74HC4075M -55 to 125 14 Ld SOIC M14.15
CD74HC4075M -55 to 125 14 Ld SOIC M14.15
CD54HC4075H -55 to 125 Die
CD54HCT4075H -55 to 125 Die
CD54HC4075W -55 to 125 Wafer
CD54HCT4075W -55 to 125 Wafer

NO.

Pinout

NOTE: When ordering, usethe entire partnumber.Add the suffix 96
to obtain the variant in the tape and reel.

CD74HC4075, CD74HCT4075

(PDIP, SOIC)

TOP VIEW

2A
2B
1A
1B
1C
1C

GND

1
2
3
4
5
6
7

V

14

CC

3C

13

3B

12

3A

11

3Y

10

2Y

9

2C

8

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

1

File Number 1778.1

Functional Diagram

CD74HC4075, CD74HCT4075

3

1A

4

1B

5

1C

1

2A

2

2B

8

2C

11

3A

12

3B

13

3C

TRUTH TABLE

INPUTS OUTPUT

nA nB nC nY

6

1Y

9

2Y

10

3Y

GND = 7
V

= 14

CC

Logic Diagram

LLLL
HXXH
XHXH
XXHH

NOTE: H = High Voltage Level, L = Low Voltage Level, X = Irrelevant

nA

nB

nC

nY

2