TEXAS INSTRUMENTS CD54HC4075 Technical data

Data sheet acquired from Harris Semiconductor
SCHS210G

August 1997 - Revised June 2006

CD54HC4075, CD74HC4075,

CD54HCT4075, CD74HCT4075

High-Speed CMOS Logic

Triple 3-Input OR Gate

[ /Title
(CD74H
C4075,
CD74H
CT4075)
/Subject
(High
Speed
CMOS
Logic
Triple 3­Input

Features

• Buffered Inputs

• Typical Propagation Delay: 8ns at V
C

= 15pF, TA = 25oC

L

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

CC

= 5V,

o

C to 125oC

OH

Description

The ’HC4075 and ’HCT4075 logic gates utilize silicon-gate
CMOS technology to achieve operating speeds similar to
LSTTL gates with the low power consumption of standard
CMOS integratedcircuits. All devices have the ability to drive
10 LSTTL loads. The HCT logic family is functionally pin
compatible with the standard LS logic family.

Ordering Information

TEMP. RANGE

CC

PART NUMBER

CD54HC4075F3A -55 to 125 14 Ld CERDIP
CD54HC4075FK -55 to 125 20 LCCC
CD54HCT4075F3A -55 to 125 14 Ld CERDIP
CD74HC4075E -55 to 125 14 Ld PDIP
CD74HC4075M -55 to 125 14 Ld SOIC
CD74HC4075MT -55 to 125 14 Ld SOIC
CD74HC4075M96 -55 to 125 14 Ld SOIC
CD74HC4075NSR -55 to 125 14 Ld SOP
CD74HC4075PW -55 to 125 14 Ld TSSOP

(oC) PACKAGE

CD74HC4075PWR -55 to 125 14 Ld TSSOP
CD74HC4075PWT -55 to 125 14 Ld TSSOP
CD74HCT4075E -55 to 125 14 Ld PDIP

NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© 2006, Texas Instruments Incorporated

1

Pinout

CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075

CD54HC4075, CD54HCT4075 (CERDIP)

CD74HC4075 (PDIP, SOIC, SOP, TSSOP)

CD74HCT4075 (PDIP)

TOP VIEW

1A

NC

2A
2B
1A
1B
1C
1Y

GND

1
2
3
4
5
6
7

14
13
12
11
10

9
8

SN54HC4075 (FK)

(TOP VIEW)

CC

NC

2B

2A

V

32 12019

4

5

V
3C
3B
3A
3Y
2Y
2C

CC

3C

18

17

3B

NC

1B

NC

1C

6

7

8

910 111213

1Y

GND

NC

2C

2Y

16

15

14

3A

NC

3Y

2

CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075

Functional Diagram

3

1A

1B

1C

2A

2B

2C

3A

3B
3C

4

5

1

2

8

11

12

13

6

1Y

9

2Y

10

3Y

GND = 7

= 14

V

CC

TRUTH TABLE

INPUTS OUTPUT

nA nB nC nY

Logic Diagram

LLLL
HXXH
XHXH
XXHH

H = High Voltage Level, L = Low Voltage Level, X = Irrelevant

nA

nB

nC

nY

3

CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

CC

Package Thermal Impedance, θJA(see Note 1):

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80oC/W

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86oC/W

NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76oC/W

PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 113oC/W

Maximum Junction Temperature (Hermetic Package or Die) .175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

V

IH

V

IL

V

OH

V

OL

I

I

I

CC

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

CC

(V)

o

25

C -40oC TO 85oC -55oC TO 125oC

UNITSV

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

VCC or

0 6 - - 2 - 20 - 40 µA

GND

4

CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

HCT TYPES

High Level Input
Voltage

Low Level Input

V

IH

V

IL

Voltage
High Level Output

Voltage

V

OH

CMOS Loads
High Level Output

Voltage
TTL Loads

Low Level Output

V

OL

Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

I

I

CC

∆I

CC

(Note 2)

Input Pin: 1 Unit Load

NOTE:

2. For dual-supply systems theoretical worst case (V

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

- - 4.5 to

- - 4.5 to

VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V

VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V

VCCand

GND

VCC or

GND

V

CC

-2.1

o

C -40oC TO 85oC -55oC TO 125oC

V

CC

(V)

25

UNITSV

2--2- 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

-4 4.5 3.98 - - 3.84 - 3.7 - V

4 4.5 - - 0.26 - 0.33 - 0.4 V

0 5.5 - ±0.1 - ±1-±1 µA

0 5.5 - - 2 - 20 - 40 µA

- 4.5 to

- 100 360 - 450 - 490 µA

5.5

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

HCT Input Loading Table

INPUT UNIT LOADS

All 1.6

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Table, e.g.
360µA max at 25oC.

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay,
Input to Output (Figure 1)

Transition Times (Figure 1) t

Input Capacitance C

r

t

PLH,tPHL

, t

TLH

THL

IN

, tf = 6ns

TEST

CONDITIONS VCC(V)

CL= 50pF 2 - - 100 - 125 - 150 ns

CL= 15pF 5 - 8 - - - - - ns
CL= 50pF 2 - - 75 - 95 - 110 ns

- - - - 10 - 10 - 10 pF

-40oC TO

25oC

85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

4.5 - - 20 - 25 - 30 ns
6 - - 17 - 21 - 26 ns

4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns

5

Switching Specifications Input t

, tf = 6ns (Continued)

r

TEST

PARAMETER SYMBOL

Power Dissipation Capacitance

C

CONDITIONS VCC(V)

PD

-5-26-----pF

(Notes 3, 4)

HCT TYPES

Propagation Delay, Input to
Output (Figure 2)

Transition Times (Figure 2) t
Input Capacitance C
Power Dissipation Capacitance

t

PLH

TLH

, t

CL= 50pF 4.5 - - 24 - 30 - 36 ns

PHL

CL= 15pF 5 - 9 - - - - - ns

, t

IN

C

PD

CL= 50pF 4.5 - - 15 - 19 - 22 ns

THL

- - - - 10 - 10 - 10 pF

-5-28-----pF

(Notes 3, 4)

NOTES:

3. CPD is used to determine the dynamic power consumption, per gate.

4. PD = V

2

fi(CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

CC

Test Circuits and Waveforms

25oC

-40oC TO
85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

tr = 6ns tf = 6ns

V

t

TLH

CC

GND

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

90%
50%
10%

t

90%

50%

10%

PLH

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

= 6ns

t

PLH

t

f

1.3V

10%

t

90%

3V

GND

TLH

tr = 6ns

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

2.7V

1.3V

0.3V

FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

6