TEXAS INSTRUMENTS CD54HC4075 Technical data

Data sheet acquired from Harris Semiconductor
SCHS210G

August 1997 - Revised June 2006

CD54HC4075, CD74HC4075,

CD54HCT4075, CD74HCT4075

High-Speed CMOS Logic

Triple 3-Input OR Gate

[ /Title
(CD74H
C4075,
CD74H
CT4075)
/Subject
(High
Speed
CMOS
Logic
Triple 3­Input

Features

• Buffered Inputs

• Typical Propagation Delay: 8ns at V
C

= 15pF, TA = 25oC

L

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

CC

= 5V,

o

C to 125oC

OH

Description

The ’HC4075 and ’HCT4075 logic gates utilize silicon-gate
CMOS technology to achieve operating speeds similar to
LSTTL gates with the low power consumption of standard
CMOS integratedcircuits. All devices have the ability to drive
10 LSTTL loads. The HCT logic family is functionally pin
compatible with the standard LS logic family.

Ordering Information

TEMP. RANGE

CC

PART NUMBER

CD54HC4075F3A -55 to 125 14 Ld CERDIP
CD54HC4075FK -55 to 125 20 LCCC
CD54HCT4075F3A -55 to 125 14 Ld CERDIP
CD74HC4075E -55 to 125 14 Ld PDIP
CD74HC4075M -55 to 125 14 Ld SOIC
CD74HC4075MT -55 to 125 14 Ld SOIC
CD74HC4075M96 -55 to 125 14 Ld SOIC
CD74HC4075NSR -55 to 125 14 Ld SOP
CD74HC4075PW -55 to 125 14 Ld TSSOP

(oC) PACKAGE

CD74HC4075PWR -55 to 125 14 Ld TSSOP
CD74HC4075PWT -55 to 125 14 Ld TSSOP
CD74HCT4075E -55 to 125 14 Ld PDIP

NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© 2006, Texas Instruments Incorporated

1

Pinout

CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075

CD54HC4075, CD54HCT4075 (CERDIP)

CD74HC4075 (PDIP, SOIC, SOP, TSSOP)

CD74HCT4075 (PDIP)

TOP VIEW

1A

NC

2A
2B
1A
1B
1C
1Y

GND

1
2
3
4
5
6
7

14
13
12
11
10

9
8

SN54HC4075 (FK)

(TOP VIEW)

CC

NC

2B

2A

V

32 12019

4

5

V
3C
3B
3A
3Y
2Y
2C

CC

3C

18

17

3B

NC

1B

NC

1C

6

7

8

910 111213

1Y

GND

NC

2C

2Y

16

15

14

3A

NC

3Y

2

CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075

Functional Diagram

3

1A

1B

1C

2A

2B

2C

3A

3B
3C

4

5

1

2

8

11

12

13

6

1Y

9

2Y

10

3Y

GND = 7

= 14

V

CC

TRUTH TABLE

INPUTS OUTPUT

nA nB nC nY

Logic Diagram

LLLL
HXXH
XHXH
XXHH

H = High Voltage Level, L = Low Voltage Level, X = Irrelevant

nA

nB

nC

nY

3

CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

CC

Package Thermal Impedance, θJA(see Note 1):

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80oC/W

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86oC/W

NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76oC/W

PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 113oC/W

Maximum Junction Temperature (Hermetic Package or Die) .175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

V

IH

V

IL

V

OH

V

OL

I

I

I

CC

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

CC

(V)

o

25

C -40oC TO 85oC -55oC TO 125oC

UNITSV

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

VCC or

0 6 - - 2 - 20 - 40 µA

GND

4

CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

HCT TYPES

High Level Input
Voltage

Low Level Input

V

IH

V

IL

Voltage
High Level Output

Voltage

V

OH

CMOS Loads
High Level Output

Voltage
TTL Loads

Low Level Output

V

OL

Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

I

I

CC

∆I

CC

(Note 2)

Input Pin: 1 Unit Load

NOTE:

2. For dual-supply systems theoretical worst case (V

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

- - 4.5 to

- - 4.5 to

VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V

VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V

VCCand

GND

VCC or

GND

V

CC

-2.1

o

C -40oC TO 85oC -55oC TO 125oC

V

CC

(V)

25

UNITSV

2--2- 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

-4 4.5 3.98 - - 3.84 - 3.7 - V

4 4.5 - - 0.26 - 0.33 - 0.4 V

0 5.5 - ±0.1 - ±1-±1 µA

0 5.5 - - 2 - 20 - 40 µA

- 4.5 to

- 100 360 - 450 - 490 µA

5.5

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

HCT Input Loading Table

INPUT UNIT LOADS

All 1.6

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Table, e.g.
360µA max at 25oC.

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay,
Input to Output (Figure 1)

Transition Times (Figure 1) t

Input Capacitance C

r

t

PLH,tPHL

, t

TLH

THL

IN

, tf = 6ns

TEST

CONDITIONS VCC(V)

CL= 50pF 2 - - 100 - 125 - 150 ns

CL= 15pF 5 - 8 - - - - - ns
CL= 50pF 2 - - 75 - 95 - 110 ns

- - - - 10 - 10 - 10 pF

-40oC TO

25oC

85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

4.5 - - 20 - 25 - 30 ns
6 - - 17 - 21 - 26 ns

4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns

5

Switching Specifications Input t

, tf = 6ns (Continued)

r

TEST

PARAMETER SYMBOL

Power Dissipation Capacitance

C

CONDITIONS VCC(V)

PD

-5-26-----pF

(Notes 3, 4)

HCT TYPES

Propagation Delay, Input to
Output (Figure 2)

Transition Times (Figure 2) t
Input Capacitance C
Power Dissipation Capacitance

t

PLH

TLH

, t

CL= 50pF 4.5 - - 24 - 30 - 36 ns

PHL

CL= 15pF 5 - 9 - - - - - ns

, t

IN

C

PD

CL= 50pF 4.5 - - 15 - 19 - 22 ns

THL

- - - - 10 - 10 - 10 pF

-5-28-----pF

(Notes 3, 4)

NOTES:

3. CPD is used to determine the dynamic power consumption, per gate.

4. PD = V

2

fi(CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

CC

Test Circuits and Waveforms

25oC

-40oC TO
85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

tr = 6ns tf = 6ns

V

t

TLH

CC

GND

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

90%
50%
10%

t

90%

50%

10%

PLH

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

= 6ns

t

PLH

t

f

1.3V

10%

t

90%

3V

GND

TLH

tr = 6ns

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

2.7V

1.3V

0.3V

FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

6

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

5962-87722012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-8772201CA ACTIVE CDIP J 14 1 TBD A42SNPB N / A for Pkg Type

CD54HC4075F3A ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type

CD54HC4075FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type

CD54HCT4075F3A ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type

CD74HC4075E ACTIVE PDIP N 14 25 Pb-Free

CD74HC4075EE4 ACTIVE PDIP N 14 25 Pb-Free

CD74HC4075M ACTIVE SOIC D 14 50 Green (RoHS &

CD74HC4075M96 ACTIVE SOIC D 14 2500 Green (RoHS &

CD74HC4075M96E4 ACTIVE SOIC D 14 2500 Green (RoHS &

CD74HC4075M96G4 ACTIVE SOIC D 14 2500 Green (RoHS &

CD74HC4075ME4 ACTIVE SOIC D 14 50 Green (RoHS &

CD74HC4075MG4 ACTIVE SOIC D 14 50 Green (RoHS &

CD74HC4075MT ACTIVE SOIC D 14 250 Green (RoHS &

CD74HC4075MTE4 ACTIVE SOIC D 14 250 Green (RoHS &

CD74HC4075MTG4 ACTIVE SOIC D 14 250 Green (RoHS &

CD74HC4075NSR ACTIVE SO NS 14 2000 Green (RoHS &

CD74HC4075NSRG4 ACTIVE SO NS 14 2000 Green (RoHS &

CD74HC4075PW ACTIVE TSSOP PW 14 90 Green (RoHS &

CD74HC4075PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS &

CD74HC4075PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS &

CD74HC4075PWR ACTIVE TSSOP PW 14 2000 Green (RoHS &

CD74HC4075PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS &

CD74HC4075PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &

CD74HC4075PWT ACTIVE TSSOP PW 14 250 Green (RoHS &

CD74HC4075PWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS &

CD74HC4075PWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS &

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

(RoHS)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU N / A for Pkg Type

CU NIPDAU N / A for Pkg Type

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

9-Oct-2007

(3)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

CD74HCT4075E ACTIVE PDIP N 14 25 Pb-Free

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU N / A for Pkg Type

9-Oct-2007

(3)

(RoHS)

CD74HCT4075EE4 ACTIVE PDIP N 14 25 Pb-Free

CU NIPDAU N / A for Pkg Type

(RoHS)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

TAPE AND REEL INFORMATION

11-Mar-2008

*All dimensions are nominal

Device Package

Type

CD74HC4075M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD74HC4075NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

CD74HC4075PWR TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1

Package
Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

CD74HC4075M96 SOIC D 14 2500 346.0 346.0 33.0

CD74HC4075NSR SO NS 14 2000 346.0 346.0 33.0

CD74HC4075PWR TSSOP PW 14 2000 346.0 346.0 29.0

Pack Materials-Page 2

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

1,20 MAX

14

0,30
0,19

8

4,50
4,30

PINS **

7

Seating Plane

0,15
0,05

8

1

A

DIM

14

0,10

6,60
6,20

M

0,10

0,15 NOM

0°–8°

2016

Gage Plane

24

0,25

0,75
0,50

28

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

4040064/F 01/97

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A SQ

B SQ

19

20

21

22

23

24

25

12826 27

12

1314151618 17

0.020 (0,51)

0.010 (0,25)

MIN

0.342
(8,69)

0.442

0.640

0.739

0.938

1.141

A

0.358
(9,09)

0.458

(11,63)

0.660

(16,76)

0.761

(19,32)(18,78)

0.962

(24,43)

1.165

(29,59)

NO. OF

TERMINALS

**

11

10

9

8

7

6

5

432

20

28

44

52

68

84

0.020 (0,51)

0.010 (0,25)

(11,23)

(16,26)

(23,83)

(28,99)

MINMAX

0.307
(7,80)

0.406

(10,31)

0.495

(12,58)

0.495

(12,58)

0.850
(21,6)

1.047
(26,6)

0.080 (2,03)

0.064 (1,63)

B

MAX

0.358
(9,09)

0.458

(11,63)

0.560

(14,22)

0.560

(14,22)

0.858
(21,8)

1.063
(27,0)

0.055 (1,40)

0.045 (1,14)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

4040140/D 10/96

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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products Applications

Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive
DSP dsp.ti.com Broadband www.ti.com/broadband
Clocks and Timers www.ti.com/clocks Digital Control www.ti.com/digitalcontrol
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Military www.ti.com/military
Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security
RFID www.ti-rfid.com Telephony www.ti.com/telephony
RF/IF and ZigBee® Solutions www.ti.com/lprf Video & Imaging www.ti.com/video

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