Datasheet CD54HC4060 Datasheet (TEXAS INSTRUMENTS)

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Data sheet acquired from Harris Semiconductor
SCHS207G

February 1998 - Revised October 2003

CD54HC4060, CD74HC4060,

CD54HCT4060, CD74HCT4060

High-Speed CMOS Logic

14-Stage Binary Counter with Oscillator

/Title
CD74

C406

,

D74
CT40

0)
Sub­ect
High

peed

MOS

Features

• Onboard Oscillator

• Common Reset

• Negative-Edge Clocking

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

o

C to 125oC

OH

CC

Description

The ’HC4060 and ’HCT4060 each consist of an oscillator
section and 14 ripple-carry binary counter stages. The
oscillator configuration allows design of either RC or crystal
oscillator circuits. A Master Reset input is provided which
resets the counter to the all-0’s state and disables the
oscillator. A high levelon the MR line accomplishes the reset
function. All counter stages are master-slave flip-flops. The
state of the counter is advanced one step in binary order on

the negative transition of φI (and φO). All inputs and outputs
are buffered. Schmitt trigger action on the input-pulse-line
permits unlimited rise and fall times.

In order to achieve a symmetrical waveform in the oscillator
section the HCT4060 input pulse switch points are the same
as in the HC4060; only the MR input in the HCT4060 has
TTL switching levels.

Ordering Information

TEMP. RANGE

PART NUMBER

CD54HC4060F3A -55 to 125 16 Ld CERDIP
CD54HCT4060F3A -55 to 125 16 Ld CERDIP
CD74HC4060E -55 to 125 16 Ld PDIP
CD74HC4060M -55 to 125 16 Ld SOIC
CD74HC4060MT -55 to 125 16 Ld SOIC
CD74HC4060M96 -55 to 125 16 Ld SOIC
CD74HC4060PW -55 to 125 16 Ld TSSOP
CD74HC4060PWR -55 to 125 16 Ld TSSOP
CD74HC4060PWT -55 to 125 16 Ld TSSOP
CD74HCT4060E -55 to 125 16 Ld PDIP
CD74HCT4060M -55 to 125 16 Ld SOIC
CD74HCT4060MT -55 to 125 16 Ld SOIC
CD74HCT4060M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.

(oC) PACKAGE

Pinout

CD54HC4060, CD54HCT4060 (CERDIP)

CD74HC4060 (PDIP, SOIC, TSSOP)

CD74HCT4060 (PDIP, SOIC)

TOP VIEW

16

1

Q12

2

Q13

3

Q14

4

Q6

5

Q5

6

Q7

7

Q4

8

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© 2003, Texas Instruments Incorporated

1

V

CC

15

Q10

14

Q8

13

Q9

12

MR
φI

11
10

φO

9

φO

Functional Diagram

CD54/74HC4060, CD54/74HCT4060

7

Q4

5

Q5

MR

φO
φO

12

14-STAGE

RIPPLE

COUNTER

11

φI

9

10

AND

OSCILLATOR

4
6
14
13
15
1
2
3

GND = 8

V

= 16

CC

Q6
Q7
Q8
Q9
Q10
Q12
Q13
Q14

øO
øO

ø1

MR

9

ø1Q1

10
11

FF1

ø1 Q1

R

12

ø4Q4

FF4

ø4 Q4

R

Q13

ø14 Q14

FF14

ø14 Q14

R

Q14

ø5 Q13

FF5 - FF13

ø5 Q13

R

723

5, 4, 6, 14, 13, 15, 1

Q4

Q5 - Q10, Q12

FIGURE 1. LOGIC BLOCK DIAGRAM

TRUTH TABLE

øI MR OUTPUT STATE

↑ L No Change
↓ L Advance to Next State

X H All Outputs are Low

2

CD54/74HC4060, CD54/74HCT4060

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

CC

Thermal Resistance (Typical, Note 1) θJA (oC/W)

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73

PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . 108

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage Q Outputs
CMOS Loads

High Level Output
Voltage Q Outputs
TTL Loads

Low Level Output
Voltage Q Outputs
CMOS Loads

Low Level Output
Voltage Q Outputs
TTL Loads

High-Level Output
Voltage

φO Output
(Pin 10)
CMOS Loads

V

IH

V

IL

V

OH

V

OL

V

OH

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

CC

(V)

o

25

C -40oC TO 85oC -55oC TO 125oC

UNITSV

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - - V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

GND

-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

3

CD54/74HC4060, CD54/74HCT4060

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

High-Level Output
Voltage φO Output
(Pin 10)
TTL Loads
(Note 2)

Low-Level Output
Voltage

φO Output
(Pin 10)
CMOS Loads

Low-Level Output
Voltage

φO Output
(Pin 10)
TTL Loads

High-Level Output
Voltage φO Output
(Pin 9)
TTL Loads

Low-Level Output
Voltage φO Output
(Pin 9)
TTL Loads

Input Leakage
Current

Quiescent Device
Current

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage Q Outputs
CMOS Loads

High Level Output
Voltage Q Outputs
TTL Loads

Low Level Output
Voltage Q Outputs
CMOS Loads

Low Level Output
Voltage Q Outputs
TTL Loads

High-Level Output
Voltage φO Output
(Pin 10)
CMOS Loads

High-Level Output
Voltage

φO Output
(Pin 10)
TTL Loads (Note 2)

Low-Level Output
Voltage

φO Output
(Pin 10)
CMOS Loads

V

OH

V

OL

V

OL

V

OH

V

OL

I

I

I

CC

V

IH

V

IL

V

OH

V

OL

V

OH

V

OH

V

OL

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

VCC or

GND

VCC or

GND

VCC or

GND

VILor V

IH

VILor V

IH

VCC or

GND

VCC or

GND

- - 4.5 to

- - 4.5 to

VIHor V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

IL

(Note 3)

VIHor V

IL

(Note 3)

VCC or

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

GND

VCC or

GND

VCC or

GND

o

C -40oC TO 85oC -55oC TO 125oC

V

CC

(V)

25

UNITSV

-2.6 4.5 3.98 - - 3.84 - 3.7 - V

-3.3 6 5.48 - - 5.34 - 5.2 - V

0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

2.6 4.5 - - 0.26 - 0.33 - 0.4 V

3.3 6 - - 0.26 - 0.33 - 0.4 V

-3.2 4.5 3.98 - - 3.84 - 3.7 - V

-4.2 6 5.48 - - 5.34 - 5.2 - V

-2.6 4.5 - - 0.26 - 0.33 - 0.4 V

-3.3 6 - - 0.26 - 0.33 - 0.4 V

-6--±0.1 - ±1-±1 µA

0 6 - - 8 - 80 - 160 µA

2--2- 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

-4 4.5 3.98 - - 3.84 - 3.7 - V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

4 4.5 - - 0.26 - 0.33 - 0.4 V

-2.6 4.5 3.98 - - 3.84 - 3.7 - V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

4

CD54/74HC4060, CD54/74HCT4060

DC Electrical Specifications (Continued)

TEST

PARAMETER SYMBOL

Low-Level Output
Voltage φO Output

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

OL

VCC or

2.6 4.5 - - 0.26 - 0.33 - 0.4 V

GND

V

CC

(V)

(Pin 10)
TTL Loads

High-Level Output

OH

VILor V

V

-3.2 4.5 3.98 - - 3.84 - 3.7 - V

IH

Voltage φO Output
(Pin 9)
TTL Loads

Low-Level Output
Voltage φO Output

V

OL

VIHor V

3.2 4.5 - 0.26 - 0.33 - 0.4 V

IL

(Note 3)
(Pin 9)
TTL Loads

Input Leakage
Current

I

I

Any

- 5.5 - ±0.1 - ±1-±1 µA

Voltage
Between
VCCand

GND

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

CC

∆I

CC

(Note 4)

VCC or

GND

V

CC

- 2.1

0 5.5 - - 8 - 80 - 160 µA

- 4.5 to

- 100 360 - 450 - 490 µA

5.5

Input Pin: 1 Unit Load

NOTES:

2. Limits not valid when pin 12 (instead of pin 11) is used as control input.

3. For pin 11 V

= 3.15V, VIL = 0.9V.

IH

4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

o

C -40oC TO 85oC -55oC TO 125oC

25

UNITSV

HCT Input Loading Table

INPUT UNIT LOADS

MR 0.35

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Specifica­tions Table, e.g. 360µA max at 25oC.

Prerequisite for Switching Specifications

25oC -40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL VCC(V)

HC TYPES

Maximum Input Pulse
Frequency

Input Pulse Width t

Reset Removal Time t

f

max

W

REM

2 6 - - 5 - - 4 - - MHz

4.5 30 - - 25 - - 20 - - MHz
6 35 - - 29 - - 23 - - MHz
2 80 - - 100 - - 120 - - ns

4.5 16 - - 20 - - 24 - - ns
614--17- -20--ns
2 100 - - 125 - - 150 - - ns

4.5 20 - - 25 - - 30 - - ns
617--21- -26--ns

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

5

CD54/74HC4060, CD54/74HCT4060

Prerequisite for Switching Specifications (Continued)

25oC -40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL VCC(V)

Reset Pulse Width t

HCT TYPES

Maximum Input,
Pulse Frequency

Input Pulse Width t
Reset Removal Time t
Reset Pulse Width t

W

f

max

W

REM

W

2 80 - - 100 - - 120 - - ns

4.5 16 - - 20 - - 24 - - ns
614--17- -20--ns

4.5 30 - - 25 - - 20 - - MHz

4.5 16 - - 20 - - 24 - - ns

4.5 26 - - 33 - - 39 - - ns

4.5 25 - - 31 - - 38 - - ns

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

Switching Specifications Input t

PARAMETER SYMBOL

, tf= 6ns

r

TEST

CONDITIONS VCC(V)

25oC

-40oC TO
85oC

-55oC TO
125oC

HC TYPES

Propagation Delay

PLH

, t

PHL

CL = 50pF

2 - - 300 - 375 - 450 ns

t

φI to Q4 4.5 - - 60 - 75 - 90 ns

CL = 15pF 5 - 25 - - - - - ns
CL = 50pF 6 - - 51 - 64 - 78 ns

Qn to Q

n+1

t

PLH

, t

CL = 50pF 2 - - 80 - 100 - 120 ns

PHL

4.5 - - 16 - 20 - 24 ns
CL = 15pF 5 - 6 - - - - - ns
CL = 50pF 6 - - 14 - 17 - 20 ns

MR to Q

n

t

PHL

CL = 50pF 2 - - 175 - 220 - 265 ns

4.5 - - 35 - 44 - 53 ns
CL = 15pF 5 - 14 - - - - - ns
CL = 50pF 6 - - 30 - 37 - 45 ns

Output Transition Time t

THL

, t

CL = 50pF 2 - - 75 - 95 - 110 ns

TLH

4.5 - - 15 - 19 - 22 ns

6 - - 13 - 16 - 19 ns

Input Capacitance C

I

(TBD)

Propagation Dissipation

C

PD

---40-----pF

Capacitance (Notes 5, 6)

HCT TYPES

Propagation Delay

PLH

, t

PHL

CL = 50pF

2

- - - - - - - -ns

t

φI to Q4 4.5 - - 66 - 83 - 100 ns

CL = 15pF 5 - 25 - - - - - -ns
CL = 50pF 6 - - - - - - - -ns

UNITSMIN TYP MAX MIN MAX MIN MAX

6

CD54/74HC4060, CD54/74HCT4060

Switching Specifications Input t

, tf= 6ns (Continued)

r

TEST

PARAMETER SYMBOL

Qn to Q

n+1

t

PLH

CONDITIONS VCC(V)

, t

CL = 50pF 2 - - - - - - - ns

PHL

4.5 - - 16 - 20 - 24 ns
CL = 15pF 5 - 6 - - - - - ns
CL = 50pF 6 - - - - - - - ns

MR to Q

n

t

PHL

CL = 50pF 2 - - - - - - - ns

4.5 - - 44 - 55 - 66 ns
CL = 15pF 5 - 17 - - - - - ns
CL = 50pF 6 - - - - - - - ns

Output Transition Time t

THL

, t

CL = 50pF 2 - - - - - - - ns

TLH

4.5 - - 15 - 19 - 22 ns

6-------ns

Input Capacitance C

I

(TBD)

Propagation Dissipation

C

PD

---40-----pF

Capacitance (Notes 5, 6)

NOTES:

5. CPD is used to determine the dynamic power consumption, per package.

6. PD = CPD V

CC

2

fi∑(CL V

2

fi/M) where M = 21, 22, 23, ...214, fi = input frequency, CL = output load capacitance.

CC

25oC

-40oC TO
85oC

-55oC TO
125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

TYPICAL LIMIT VALUES FOR RX AND C

X

TYPICAL

PARAMETER

TEST

CONDITIONS VOLTAGE

MAXIMUM

LIMITS

RX Minimum CX > 1000pF 2 1KΩ

CX > 10pF 4.5
CX > 10pF 6

RX Maximum CX > 10pF 2 20MΩ

CX > 10pF 4.5
CX > 10pF 6

CX Minimum RX > 10KΩ 2 10pF

RX > 10KΩ 4.5
RX > 10KΩ 6
RX = 1KΩ 2 1000pF
RX = 1KΩ 4.5 10pF
RX = 1KΩ 6 10pF

Maximum
Astable Oscillator
Frequency

CX = 1000pF,
RX = 1KΩ

CX = 100pF,
RX = 1KΩ

CX = 100pF,
RX = 1KΩ

2 0.5MHz

(Note 7)

4.5 3MHz
(Note 7)

6 3MHz

(Note 7)

NOTE:

7. At very high frequencies f = 1/2.2 RXCXno longer gives an
accurate approximation.

2

10

10

1

-1

10

(µF)

X

-2

C

10

-3

10

-4

10

-5

10

-1

0

10

10

10

OSCILLATOR FREQUENCY (Hz)

10

NOTE: OSC Frequency ≈ 1/2.2 RXC

3

2

10

X

10

TA = 25oC
RX = 1KΩ
10KΩ
100KΩ
1MΩ
10MΩ

4

10510

For 1MΩ > RX > 1KΩ, CX > 10pF, f < 1MHz

FIGURE 2. FREQUENCY OF ON-BOARD OSCILLATOR AS A

FUNCTION OF CX AND R

X

6

7

CD54/74HC4060, CD54/74HCT4060

Typical Performance Curves

I

fC

50%

L

V

CC

GND

trC

L

CLOCK

10%

90%

50%

10%

tfC

t

WL

t

+ tWH=

50%

WL

t

WH

L

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table.For f

, input duty cycle = 50%.

MAX

FIGURE 3. HC CLOCK PULSE RISE AND FALLTIMES AND

PULSE WIDTH

tr = 6ns tf = 6ns

V

t

CC

GND

TLH

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

90%
50%
10%

t

90%

50%

10%

PLH

1.3V

I

fC

L

3V

GND

t

rCL

CLOCK

= 6ns

0.3V

2.7V

1.3V

0.3V

t

fCL

t

WL

= 6ns

1.3V

t

WH

t

WL

+ tWH=

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table.For f

, input duty cycle = 50%.

MAX

FIGURE 4. HCT CLOCK PULSE RISE AND FALLTIMES AND

PULSE WIDTH

= 6ns

t

PLH

t

f

10%

90%

1.3V

t

3V

GND

TLH

tr = 6ns

INPUT

t

INVERTING

OUTPUT

THL

t

2.7V

1.3V

0.3V

PHL

FIGURE 5. HC AND HCT TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

FIGURE 6. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

8

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

5962-8768001EA ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type
5962-8977101EA ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type

CD54HC4060F3A ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type

CD54HCT4060F3A ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type

CD74HC4060E ACTIVE PDIP N 16 25 Pb-Free

CD74HC4060EE4 ACTIVE PDIP N 16 25 Pb-Free

CD74HC4060M ACTIVE SOIC D 16 40 Green (RoHS &

CD74HC4060M96 ACTIVE SOIC D 16 2500 Green (RoHS &

CD74HC4060M96E4 ACTIVE SOIC D 16 2500 Green (RoHS &

CD74HC4060ME4 ACTIVE SOIC D 16 40 Green (RoHS &

CD74HC4060MT ACTIVE SOIC D 16 250 Green (RoHS &

CD74HC4060MTE4 ACTIVE SOIC D 16 250 Green (RoHS &

CD74HC4060PW ACTIVE TSSOP PW 16 90 Green(RoHS &

CD74HC4060PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS &

CD74HC4060PWR ACTIVE TSSOP PW 16 2000 Green (RoHS &

CD74HC4060PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS &

CD74HC4060PWT ACTIVE TSSOP PW 16 250 Green (RoHS &

CD74HC4060PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS &

CD74HCT4060E ACTIVE PDIP N 16 25 Pb-Free

CD74HCT4060EE4 ACTIVE PDIP N 16 25 Pb-Free

CD74HCT4060M ACTIVE SOIC D 16 40 Green (RoHS &

CD74HCT4060M96 ACTIVE SOIC D 16 2500 Green (RoHS &

CD74HCT4060M96E4 ACTIVE SOIC D 16 2500 Green (RoHS &

CD74HCT4060ME4 ACTIVE SOIC D 16 40 Green (RoHS &

CD74HCT4060MT ACTIVE SOIC D 16 250 Green (RoHS &

CD74HCT4060MTE4 ACTIVE SOIC D 16 250 Green (RoHS &

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU N / A for Pkg Type

CU NIPDAU N / A for Pkg Type

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU N / A for Pkg Type

CU NIPDAU N / A for Pkg Type

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

12-Jan-2006

(3)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

(1)

The marketing status values are defined as follows:

12-Jan-2006

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

1,20 MAX

14

0,30
0,19

8

4,50
4,30

PINS **

7

Seating Plane

0,15
0,05

8

1

A

DIM

14

0,10

6,60
6,20

M

0,10

0,15 NOM

0°–8°

2016

Gage Plane

24

0,25

0,75
0,50

28

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

4040064/F 01/97

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