Texas Instruments CD74HCT4053PWR, CD74HCT4053M96, CD74HCT4053M, CD74HCT4053E, CD74HCT4052M96 Datasheet

Data sheet acquired from Harris Semiconductor
SCHS122A

November 1997 - Revised April 1999

CD54HC4051,
CD74HC4051, CD74HCT4051,
CD74HC4052, CD74HCT4052,

CD74HC4053, CD74HCT4053

High Speed CMOS Logic

Analog Multiplexers/Demultiplexers

[ /Title
(CD54
HC405
1,
CD74
HC405
1,
CD74
HCT40
51,
CD74
HC405
2,

Features

• Wide Analog Input Voltage Range . . . . . . . . . . ±5V Max

• Low “On” Resistance

-70Ω Typical (V

-40Ω Typical (V

• Low Crosstalk between Switches

• Fast Switching and Propagation Speeds

• “Break-Before-Make” Switching

• Wide Operating Temperature Range . . -55

• CD54HC/CD74HC Types

- Operation Control Voltage . . . . . . . . . . . . . . 2V to 6V

- Switch Voltage . . . . . . . . . . . . . . . . . . . . . . .0V to 10V

- High Noise Immunity . . . N
V

= 5V

CC

• CD54HCT/CD74HCT Types

- Operation Control Voltage . . . . . . . . . . . 4.5V to 5.5V

- Switch Voltage . . . . . . . . . . . . . . . . . . . . . . . 0V to 10V

- Direct LSTTL Input
Logic Compatibility . . . V

- CMOS Input Compatibility. . . . . I

- VEE = 4.5V)

CC

- VEE = 9V)

CC

o

C to 125oC

= 30%, NIH = 30% of VCC,

IL

= 0.8V Max, VIH = 2V Min

IL

≤ 1µA at VOL, V

I

OH

Description

These devices are digitally controlled analog switches which
utilize silicon gate CMOS technology to achieve operating
speeds similar to LSTTL with the low power consumption of
standard CMOS integrated circuits.

These analog multiplexers/demultiplexers control analog
voltages that may vary across the voltage supply range (i.e.
V

to VEE). They are bidirectional switches thus allowing

CC

any analog input to be used as an output and visa-versa.
The switches have low “on” resistance and low “off” leak­ages. In addition, all three devices have an enable control
which, when high, disables all switches to their “off” state.

Ordering Information

TEMP.

PART NUMBER

CD54HC4051F -55 to 125 16 Ld CERDIP F16.3
CD74HC4051E -55 to 125 16 Ld PDIP E16.3
CD74HC4052E -55 to 125 16 Ld PDIP E16.3
CD74HC4053E -55 to 125 16 Ld PDIP E16.3
CD74HCT4051E -55 to 125 16 Ld PDIP E16.3
CD74HCT4052E -55 to 125 16 Ld PDIP E16.3
CD74HCT4053E -55 to 125 16 Ld PDIP E16.3
CD74HC4051M -55 to 125 16 Ld SOIC M16.15
CD74HC4052M -55 to 125 16 Ld SOIC M16.15
CD74HC4053M -55 to 125 16 Ld SOIC M16.15
CD74HCT4051M -55 to 125 16 Ld SOIC M16.15
CD74HCT4052M -55 to 125 16 Ld SOIC M16.15
CD74HCT4053M -55 to 125 16 Ld SOIC M16.15
CD74HCT4053PW -55 to 125 16 Ld TSSOP
CD74HCT4052SM -55 to 125 16 Ld SSOP M16.15A

NOTES:

1. When ordering, usethe entire part number. Add thesuffix 96to
obtain the variant in the tape and reel. For the TSSOP package
only, add the suffix R to obtain the variant in the tape and reel.

2. Waferor die is available which meets all electrical specifications.
Please contact your local salesoffice or Harris customerservice
for ordering information.

RANGE (oC) PACKAGE

PKG.

NO.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

1

File Number 1676.1

Pinouts

CD54HC4051, CD74HC4051, 52, 53; CD74HCT4051, 52, 53

CHANNEL

IN/OUT

COM OUT/IN

CHANNEL

IN/OUT

CD54HC4051

CD74HC4051, CD74HCT4051

(CERDIP, PDIP, SOIC)

TOP VIEW

16

A4
A6

A7
A5

V

EE

GND

1
2

A

3
4
5
6

E

7
8

V
A2

15
14

A1

13

A0

12

A3
S0

11
10

S1
S2

9

CHANNEL

COM OUT/IN

CC

IN/OUT

IN/OUT

CHANNEL
IN/OUT

ADDRESS
SELECT

CD74HC4053, CD74HCT4053

(PDIP, SOIC, TSSOP)

TOP VIEW

1

B1

2

B0
C1

3

C

4

N

5

C0

6

E

7

V

EE

8

GND

CHANNEL

IN/OUT

COM OUT/IN

CHANNEL

IN/OUT

16

V

CC

15

B

N

14

A

N

13

A1

12

A0
S0

11
10

S1
S2

9

CD74HC4052, CD74HCT4052

(PDIP, SOIC)

TOP VIEW

1

B0

2

B2
B

3

N

4

B3

5

B1

6

E

7

V

EE

8

GND

COM OUT/IN

COM OUT/IN

CHANNEL
IN/OUT

16

V

CC

A2

15
14
13
12
11
10

9

A1
A
A0
A3
S0
S1

N

CHANNEL
IN/OUT

COM OUT/IN

CHANNEL
IN/OUT

2

CD54HC4051, CD74HC4051, 52, 53; CD74HCT4051, 52, 53CD54HC4051, CD74HC4051, 52, 53; CD74HCT4051, 52, 53

Functional Diagram of HC/HCT4051

CHANNEL IN/OUT

V

CC

16

S

11

0

10

S

1

LOGIC

LEVEL

CONVERSION

S

9

2

6E

BINARY

TO

1 OF 8

DECODER

WITH

ENABLE

A

7A6A5A4A3A2A1A0

131415121524

TG

TG

TG

TG

TG

TG

TG

TG

3

A
COMMON
OUT/IN

8 7

GND V

X = Don’t care

EE

TRUTH TABLE

CD54/74HC/HCT4051

INPUT STATES

“ON”

2

S

1

S

0

CHANNELSENABLE S

L LLL A0
LLLH A1
LLHL A2
LLHH A3
LHLL A4
LHLH A5
LHHL A6
L HHH A7

H X X X None

3

CD54HC4051, CD74HC4051, 52, 53; CD74HCT4051, 52, 53CD54HC4051, CD74HC4051, 52, 53; CD74HCT4051, 52, 53

Functional Diagram of HC/HCT4052

V

CC

16

A CHANNELS IN/OUT

A

3A2A1A0

12141511

TG

TG

TG

BINARY

9

S

1

10

S

0

6E

LOGIC
LEVEL

CONVERSION

8 7

GND V

EE

TO

1 OF 4

DECODER

WITH

ENABLE

TRUTH TABLE

CD74HC4052, CD74HCT4052

INPUT STATES

1

S

0

L L L A0, B0

13

3

COMMON A
OUT/IN

COMMON B
OUT/IN

4251

B

0B1B2B3

B CHANNELS IN/OUT

TG

TG

TG

TG

TG

“ON”

CHANNELSENABLE S

L L H A1, B1
L H L A2. B2
L H H A3, B3

H X X None

X = Don’t care

4

CD54HC4051, CD74HC4051, 52, 53; CD74HCT4051, 52, 53CD54HC4051, CD74HC4051, 52, 53; CD74HCT4051, 52, 53

Functional Diagram of HC/HCT4053

LOGIC LEVEL
CONVERSION

11

S

0

10

S

1

S

9

2

6E

8

GND V

V

CC

16

7

EE

BINARY TO

1 OF 2

DECODERS

WITH ENABLE

C1C0B1B0A1A

IN/OUT

0

12132153

TG

A COMMON

14

OUT/IN

TG

TG

B COMMON

15

OUT/IN

TG

TG

C COMMON

4

OUT/IN

TG

TRUTH TABLE

CD74HC4053, CD74HCT4053

INPUT STATES

0

S

1

S

2

L L L L C0, B0, A0
L H L L C0, B0, A1
L L H L C0, B1, A0
L H H L C0, B1, A1
L L L H C1, B0, A0
L H L H C1, B0, A1
L L H H C1, B1, A0
L H H H C1, B1, A1

H X X X None

X = Don’t care

“ON”

CHANNELSENABLE S

5

CD54HC4051, CD74HC4051, 52, 53; CD74HCT4051, 52, 53CD54HC4051, CD74HC4051, 52, 53; CD74HCT4051, 52, 53

Absolute Maximum Ratings (Note 3) Thermal Information

DC Supply Voltage, VCC - VEE . . . . . . . . . . . . . . . . . -0.5V to 10.5V

DC Supply Voltage, V
DC Supply Voltage, V
DC Input Diode Current, I

CC. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V

EE . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.5V to -7V

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Switch Diode Current, I

OK

For VI < VEE -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . .±20mA

DC Switch Current, (Note 2)

For VI > VEE -0.5V or VI < VCC + 0.5V . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

DC VEE Current, IEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20mA

Recommended Operating Conditions For maximum reliability, nominal operating conditions should be selected so that

operation is always within the following ranges

PARAMETER MIN MAX UNITS

Supply Voltage Range (For T

CD54/74HC Types 26V
CD54/74HCT Types 4.5 5.5 V

Supply Voltage Range (For TA = Full Package Temperature Range), VCC - V

CD54/74HC Types, CD54/74HCT Types (See Figure 1) 2 10 V

Supply Voltage Range (For TA = Full Package Temperature Range), VEE (Note 5)

CD54/74HC Types, CD54/74HCT Types (See Figure 2) 0 -6 V
DC Input Control Voltage, V
Analog Switch I/O Voltage, V
Operating Temperature, T
Input Rise and Fall Times, tr, t

2V 0 1000 ns

4.5V 0 500 ns

6V 0 400 ns

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

3. All voltages referenced to GND unless otherwise specified.

4. θJA is measured with the component mounted on an evaluation PC board in free air.

5. Incertain applications, the external load resistor current may include both VCCandsignal line components. To avoid drawing VCCcurrent

when switch current flows into the transmission gate inputs, the voltage drop across the bidirectional switch must not exceed 0.6V (cal­culated from rONvalues shown in Electrical Specifications table). No VCCcurrent will flow through RLif the switch current flows into
terminal 3 on the HC/HCT4051; terminals 3 and 13 on the HC/HCT4052; terminals 4, 14 and 15 on the HC/HCT4053.

= Full Package Temperature Range), VCC (Note 5)

A

I

IS

A

f

Thermal Resistance (Typical, Note 4) θJA (oC/W) θJC (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . 90 N/A

SOIC Package. . . . . . . . . . . . . . . . . . . 160 N/A

CERDIP Package . . . . . . . . . . . . . . . . 130 55

TSSOP Package . . . . . . . . . . . . . . . . . 149 35

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

EE

GND V

V

EE

V

-55 125

CC
CC

V
V

o

C

Recommended Operating Area as a Function of Supply Voltages

8

6

HC

4

- GND (V)

CC

2

V

0

024681012

VCC - VEE (V)

FIGURE 1. FIGURE 2.

HCT

6

8

6

4

- GND (V)

CC

2

V

0

0-2-4-6-8

HCT

VEE - GND (V)

HC