TEXAS INSTRUMENTS CD54HC4051F3A, CD54HC4052F3A, CD54HC4053F3A, CD54HCT4051F3A, CD74HC4051E Technical data

Data sheet acquired from Harris Semiconductor
SCHS122G

November 1997 - Revised July 2003

CD54/74HC4051, CD54/74HCT4051,

CD54/74HC4052, CD74HCT4052,

CD54/74HC4053, CD74HCT4053

High-Speed CMOS Logic

Analog Multiplexers/Demultiplexers

[ /Title
(CD54
HC405
1,
CD74
HC405
1,
CD74
HCT40
51,
CD74
HC405
2,

Features

• Wide Analog Input Voltage Range . . . . . . . . . . ±5V Max

• Low “On” Resistance

-70Ω Typical (V

-40Ω Typical (V

• Low Crosstalk between Switches

• Fast Switching and Propagation Speeds

• “Break-Before-Make” Switching

• Wide Operating Temperature Range . . -55

• CD54HC/CD74HC Types

- Operation Control Voltage . . . . . . . . . . . . . . 2V to 6V

- Switch Voltage . . . . . . . . . . . . . . . . . . . . . . .0V to 10V

- High Noise Immunity . . . N
V

= 5V

CC

• CD54HCT/CD74HCT Types

- Operation Control Voltage . . . . . . . . . . . 4.5V to 5.5V

- Switch Voltage . . . . . . . . . . . . . . . . . . . . . . . 0V to 10V

- Direct LSTTL Input
Logic Compatibility . . . V

- CMOS Input Compatibility. . . . . I

- VEE = 4.5V)

CC

- VEE = 9V)

CC

o

C to 125oC

= 30%, NIH = 30% of VCC,

IL

= 0.8V Max, VIH = 2V Min

IL

≤ 1µA at VOL, V

I

OH

Description

These devices are digitally controlled analog switches which
utilize silicon gate CMOS technology to achieve operating
speeds similar to LSTTL with the low power consumption of
standard CMOS integrated circuits.

These analog multiplexers/demultiplexers control analog
voltages that may vary across the voltage supply range (i.e.
V

to VEE). They are bidirectional switches thus allowing

CC

any analog input to be used as an output and vice-versa.
The switches have low “on” resistance and low “off” leak­ages. In addition, all three devices have an enable control
which, when high, disables all switches to their “off” state.

Ordering Information

TEMP. RANGE

PART NUMBER

CD54HC4051F3A -55 to 125 16 Ld CERDIP
CD54HC4052F3A -55 to 125 16 Ld CERDIP
CD54HC4053F3A -55 to 125 16 Ld CERDIP
CD54HCT4051F3A -55 to 125 16 Ld CERDIP
CD74HC4051E -55 to 125 16 Ld PDIP
CD74HC4051M -55 to 125 16 Ld SOIC
CD74HC4051M96 -55 to 125 16 Ld SOIC
CD74HC4051NSR -55 to 125 16 Ld SOP
CD74HC4051PWR -55 to 125 16 Ld TSSOP
CD74HC4052E -55 to 125 16 Ld PDIP
CD74HC4052M -55 to 125 16 Ld SOIC
CD74HC4052M96 -55 to 125 16 Ld SOIC
CD74HC4052NSR -55 to 125 16 Ld SOP
CD74HC4052PW -55 to 125 16 Ld TSSOP
CD74HC4052PWR -55 to 125 16 Ld TSSOP
CD74HC4053E -55 to 125 16 Ld PDIP
CD74HC4053M -55 to 125 16 Ld SOIC
CD74HC4053M96 -55 to 125 16 Ld SOIC
CD74HC4053NSR -55 to 125 16 Ld SOP
CD74HC4053PW -55 to 125 16 Ld TSSOP
CD74HC4053PWR -55 to 125 16 Ld TSSOP
CD74HCT4051E -55 to 125 16 Ld PDIP
CD74HCT4051M -55 to 125 16 Ld SOIC
CD74HCT4051M96 -55 to 125 16 Ld SOIC
CD74HCT4052E -55 to 125 16 Ld PDIP
CD74HCT4052M -55 to 125 16 Ld SOIC
CD74HCT4052M96 -55 to 125 16 Ld SOIC
CD74HCT4053E -55 to 125 16 Ld PDIP
CD74HCT4053M -55 to 125 16 Ld SOIC
CD74HCT4053M96 -55 to 125 16 Ld SOIC
CD74HCT4053PWR -55 to 125 16 Ld TSSOP

NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel.

(oC) PACKAGE

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© 2003, Texas Instruments Incorporated

1

Pinouts

’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053

CHANNEL

IN/OUT

COM OUT/IN

CHANNEL

IN/OUT

CD54HC4051, CD54HCT4051

(CERDIP)

CD74HC4051

(PDIP, SOIC, SOP, TSSOP)

CD74HCT4051

(PDIP, SOIC)

TOP VIEW

16

A4
A6

A7
A5

V

EE

GND

1
2
3

A

4
5
6

E

7
8

V

15

A2

14

A1
A0

13

A3

12

S0

11

S1

10

9

S2

CHANNEL

COM OUT/IN

CC

IN/OUT

IN/OUT

CHANNEL
IN/OUT

ADDRESS
SELECT

CD54HC4053

(CERDIP)

CD74HC4053

(PDIP, SOIC, SOP, TSSOP)

CD74HCT4053

(PDIP, SOIC, TSSOP)

TOP VIEW

1

B1

2

B0

3

C1

4

C

N

5

C0

6

E

V

7

EE

8

GND

CHANNEL

IN/OUT

COM OUT/IN

CHANNEL

IN/OUT

16

V

CC

15

B

N

14

A

N

13

A1

12

A0
S0

11
10

S1

9

S2

CD54HC4052

(CERDIP)

CD74HC4052

(PDIP, SOIC, SOP, TSSOP)

CD74HCT4052

(PDIP, SOIC)

TOP VIEW

1

B0

2

B2

3

B

N

4

B3

5

B1

6

E

V

7

EE

8

GND

COM OUT/IN

COM OUT/IN

CHANNEL
IN/OUT

16

V

CC

15

A2

CHANNEL

9

A1
A
A0
A3
S0
S1

N

IN/OUT

COM OUT/IN

CHANNEL
IN/OUT

14
13
12
11
10

2

’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053

Functional Diagram of HC/HCT4051

CHANNEL IN/OUT

V

CC

16

S

11

0

10

S

1

LOGIC

LEVEL

CONVERSION

S

9

2

6E

BINARY

TO

1 OF 8

DECODER

WITH

ENABLE

A

7A6A5A4A3A2A1A0

131415121524

TG

TG

TG

TG

TG

TG

TG

TG

3

A
COMMON
OUT/IN

8 7

GND V

X = Don’t care

EE

TRUTH TABLE

HC/HCT4051

INPUT STATES

“ON”

2

S

1

S

0

CHANNELSENABLE S

L LLL A0
LLLH A1
LLHL A2
LLHH A3
LHLL A4
LHLH A5
LHHL A6
L HHH A7

H X X X None

3

’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053

Functional Diagram of ’HC4052, CD74HCT4052

V

CC

16

A CHANNELS IN/OUT

A

3A2A1A0

12141511

TG

TG

TG

BINARY

9

S

1

10

S

0

6E

LOGIC
LEVEL

CONVERSION

8 7

GND V

EE

TO

1 OF 4

DECODER

WITH

ENABLE

TRUTH TABLE

’HC4052, CD74HCT4052

INPUT STATES

1

S

0

L L L A0, B0

13

3

COMMON A
OUT/IN

COMMON B
OUT/IN

4251

B

0B1B2B3

B CHANNELS IN/OUT

TG

TG

TG

TG

TG

“ON”

CHANNELSENABLE S

L L H A1, B1
L H L A2. B2
L H H A3, B3

H X X None

X = Don’t care

4

’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053

Functional Diagram of ’HC4053, CD74HCT4053

LOGIC LEVEL
CONVERSION

11

S

0

10

S

1

S

9

2

6E

8

GND V

V

CC

16

7

EE

BINARY TO

1 OF 2

DECODERS

WITH ENABLE

C1C0B1B0A1A

IN/OUT

0

12132153

TG

A COMMON

14

OUT/IN

TG

TG

B COMMON

15

OUT/IN

TG

TG

C COMMON

4

OUT/IN

TG

TRUTH TABLE

’HC4053, CD74HCT4053

INPUT STATES

0

S

1

S

2

L L L L C0, B0, A0
L H L L C0, B0, A1
L L H L C0, B1, A0
L H H L C0, B1, A1
L L L H C1, B0, A0
L H L H C1, B0, A1
L L H H C1, B1, A0
L H H H C1, B1, A1

H X X X None

X = Don’t care

“ON”

CHANNELSENABLE S

5

’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053

Absolute Maximum Ratings (Note 2) Thermal Information

DC Supply Voltage, VCC - VEE . . . . . . . . . . . . . . . . . -0.5V to 10.5V

DC Supply Voltage, V
DC Supply Voltage, V
DC Input Diode Current, I

CC. . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V

EE . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.5V to -7V

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Switch Diode Current, I

OK

For VI < VEE -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . .±20mA

DC Switch Current, (Note 2)

For VI > VEE -0.5V or VI < VCC + 0.5V . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

DC VEE Current, IEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20mA

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

Recommended Operating Conditions For maximum reliability, nominal operating conditions should be selected so that

operation is always within the following ranges

PARAMETER MIN MAX UNITS

Supply Voltage Range (For TA = Full Package Temperature Range), VCC (Note 2)

CD54/74HC Types 26V
CD54/74HCT Types 4.5 5.5 V

Supply Voltage Range (For TA = Full Package Temperature Range), VCC - V

CD54/74HC Types, CD54/74HCT Types (See Figure 1) 2 10 V

Supply Voltage Range (For TA = Full Package Temperature Range), VEE (Note 3)

CD54/74HC Types, CD54/74HCT Types (See Figure 2) 0 -6 V
DC Input Control Voltage, V
Analog Switch I/O Voltage, V
Operating Temperature, T
Input Rise and Fall Times, tr, t

2V 0 1000 ns

4.5V 0 500 ns

6V 0 400 ns

CAUTION: Stresses abovethose listed in “Absolute Maximum Ratings” may cause permanent damage to the device.This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

2. All voltages referenced to GND unless otherwise specified..

3. Incertain applications, the external load resistor current may includeboth VCCandsignal line components. To avoid drawing VCCcurrent

when switch current flows into the transmission gate inputs, the voltage drop across the bidirectional switch must not exceed 0.6V (cal­culated from rONvalues shown in Electrical Specifications table). No VCCcurrent will flow through RLif the switch current flows into
terminal 3 on the HC/HCT4051; terminals 3 and 13 on the HC/HCT4052; terminals 4, 14 and 15 on the HC/HCT4053.

I

IS

A

f

Package Thermal Impedance, θJA(see Note 1):

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67oC/W

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73oC/W

NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64oC/W

PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .108oC/W

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

EE

GND V

V

EE

V

-55 125

CC
CC

V
V

o

C

Recommended Operating Area as a Function of Supply Voltages

8

6

HC

4

- GND (V)

CC

2

V

0

024681012

VCC - VEE (V)

FIGURE 1. FIGURE 2.

HCT

6

8

6

4

- GND (V)

CC

2

V

0

0-2-4-6-8

HCT

VEE - GND (V)

HC

’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053’HC4051, ’HCT4051, ’HC4052, CD74HCT4052, ’HC4053, CD74HCT4053

DC Electrical Specifications

TEST CONDITIONS AMBIENT TEMPERATURE, T

25oC -40oC - 85oC -55oC - 125oC

MIN TYP MAX MIN MAX MIN MAX

PARAMETER

V

(V)

V

V

IS

I

(V)

(V)

EE

V

CC

(V)

HC TYPES

High Level Input Voltage,
V

IH

2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 0 V
6 4.2 - - 4.2 - 4.2 - V

Low Level Input Voltage,
V

IL

2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

On Resistance, r

ON

IO = 1mA, (Figure 11)

VCC or V

EE

VIL or

V

IH

0 4.5 - 70 160 - 200 - 240 Ω
0 6 - 60 140 - 175 - 210 Ω

-4.5 4.5 - 40 120 - 150 - 180 Ω

VCC to V

EE

0 4.5 - 90 180 - 225 - 270 Ω
0 6 - 80 160 - 200 - 240 Ω

-4.5 4.5 - 45 130 - 162 - 195 Ω

Maximum On Resistance
Between any Two
Channels, ∆r

ON

04.5-10-----Ω
06-8.5-----Ω

-4.5 4.5 - 5 - ----Ω

Switch On/Off Leakage
Current, I

IZ

1 and 2 Channels 0 6 - - ±0.1 - ±1-±1 µA
4053 -5 5 - - ±0.1 - ±1-±1 µA

For Switch Off:
When VIS=VCC,
VOS = VEE;
When VIS=VEE,
VOS = V

CC

VIL or

V

IH

For Switch On:

4 Channels 0 6 - - ±0.1 - ±1-±1 µA
4052 -5 5 - - ±0.2 - ±2-±2 µA
8 Channels 0 6 - - ±0.2 - ±2-±2 µA

All Applicable
Combinations of
VIS and V

OS

Voltage Levels

4051 -5 5 - - ±0.4 - ±4-±4 µA

Control Input Leakage
Current, I

IL

Quiescent Device
Current, I

CC

IO = 0

When VIS=VEE,
VOS = V

CC

When VIS=VCC,
VOS = V

EE

VCC or

GND

VCC or

GND

06 - -±0.1 - ±1-±1 µA

0 6 - - 8 - 80 - 160 µA

-5 5 - - 16 - 160 - 320 µA

A

UNITS

7