Texas Instruments CD74HC4050PWR, CD74HC4050M96, CD74HC4050M, CD74HC4050E, CD74HC4049PWR Datasheet

CD74HC4049,

/
j

[ /Title
(CD74H
C4049,
CD74H
C4050)

Sub-

ect
(High
Speed
CMOS
Logic
Hex

Data sheet acquired from Harris Semiconductor
SCHS205A

February 1998 - Revised June 1999

Features

• Typical Propagation Delay: 6ns at VCC = 5V,
C

= 15pF, TA = 25oC

L

• High-to-Low Voltage Level Converter for up to V

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . .–55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

V

= 5V

CC

= 30%, NIH= 30%of VCCat

IL

o

= 16V

l

C to 125oC

CD74HC4050

High-Speed CMOS Logic

Hex Buffers, Inverting and Non-Inverting

Description

The CD74HC4049 and CD74HC4050 are fabricated with
high-speed silicon gate technology. They have a modified
input protection structure that enables these parts to be
used as logic level translators which convert high-level logic
to a low-level logic while operating off the low-level logic
supply. For example, 15-V input pulse levels can be down­converted to 0-V to 5-V logic levels. The modified input
protection structure protects the input from negative
electrostatic discharge. These parts also can be used as
simple buffers or inverters without level translation. The
CD74HC4049 and CD74HC4050 are enhanced versions of
equivalent CMOS types.

Ordering Information

TEMP. RANGE

PART NUMBER

CD74HC4049E –55 to 125 16 Ld PDIP E16.3

(oC) PACKAGE

PKG.

NO.

Pinout

CD74HC4050E –55 to 125 16 Ld PDIP E16.3
CD74HC4049M –55 to 125 16 Ld SOIC M16.15
CD74HC4050M –55 to 125 16 Ld SOIC M16.15
CD74HC4050PW –55 to 125 16 Ld TSSOP

NOTES:

1. When ordering, use the entire partnumber. Add the suffix 96 to
the M suffix or the R suffix to the PW package to obtain the
variant in the tape and reel.

2. Wafer and die is available which meets all electrical
specifications. Please contact your local sales office or
customer service for ordering information.

CD74HC4049, CD74HC4050

(PDIP, SOIC, TSSOP)

TOP VIEW

4049 4050 4050 4049

NC
6Y
6A
NC
5Y
5A
4Y
4A

NC
6Y
6A
NC
5Y
5A
4Y
4A

V

CC

1Y
1A
2Y
2A
3Y
3A

GND

V

CC

1Y
1A
2Y
2A
3Y
3A

GND

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© 1999 Texas Instruments Incorporated

1

Functional Diagram

CD74HC4049, CD74HC4050

Logic Diagrams

4050 4049 4049 4050

1Y

2Y

3Y

V

CC

1Y

1A

2Y

2A

3Y

3A

GND

1

2

3

4

5

6

7

8

16

NC

15

6Y

14

6A

13

NC

12

5Y

11

5A

10

4Y

9

4A

6Y

NC

5Y

HC4049 HC4050

A Y

AY

2

CD74HC4049, CD74HC4050

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . –0.5V to 7V

DC Input Diode Current, I

IK

For VI < –0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < –0.5V or VO > VCC + 0.5V. . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > –0.5V or VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . .–55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

Maximum Junction Temperature (Hermetic Pac kage or Die) . . .175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . –65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

V

CC

VOLTAGE

CC

RELATIONSHIPS
MAXIMUM LIMITS

V

l

+16V

+7V

DC Electrical Specifications

TEST

CONDITIONS

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

V

IL

V

OH

CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output

V

OL

Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device

I

I

CC

I

Current

NOTE: For dual-supply systems theorectical worst case (V

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

- - 2 1.5 - - 1.5 - 1.5 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

VIHor VIL–0.02 2 1.9 - - 1.9 - 1.9 - V

–0.02 4.5 4.4 - - 4.4 - 4.4 - V
–0.02 6 5.9 - - 5.9 - 5.9 - V

–4 4.5 3.98 - - 3.84 - 3.7 - V

–5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1µA

GND

15 - 6 - - ±0.5 - ±5-±5

VCC or

0 6 - - 2 - 20 - 40 µA

GND

o

25

V

CC

C –40oC TO 85oC

–55oC TO

125oC

(V)

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

UNITSV

3

CD74HC4049, CD74HC4050

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay,

t

PLH,tPHL

nA to nY HC4049
nA to nY HC4050

Transition Times (Figure 1) t

Input Capacitance C
Power Dissipation Capacitance

(Notes 4, 5)

TLH

, t

I

C

PD

NOTES:

4. C

is used to determine the dynamic power consumption, per gate.

PD

5. PD = V

2

fi(CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

CC

Test Circuit and Waveform

, tf = 6ns

r

TEST

25

o

C

–40oC TO

85oC

–55oC TO

CONDITIONS VCC(V)

CL= 50pF 2 - - 85 - 105 - 130 ns

4.5 - - 17 - 21 - 26 ns
6 - - 14 - 18 - 22 ns

C

= 15pF 5 - 6 - - - - - ns

L

CL= 50pF 2 - - 75 - 95 - 110 ns

THL

4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns

- - - - 10 - 10 - 10 pF

-5-35-----pF

125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

tr = 6ns tf = 6ns

V

t

TLH

CC

GND

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

90%
50%
10%

t

90%

50%

10%

PLH

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC

4

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1999, Texas Instruments Incorporated