TEXAS INSTRUMENTS CD54HC4049 Technical data

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Data sheet acquired from Harris Semiconductor SCHS205I

February 1998 - Revised February 2005

CD54HC4049, CD74HC4049,

CD54HC4050, CD74HC4050

High-Speed CMOS Logic

Hex Buffers, Inverting and Non-Inverting

[ /Title (CD74H C4049, CD74H C4050)

Sub-

ect (High Speed CMOS Logic Hex

Features

• Typical Propagation Delay: 6ns at VCC = 5V, C

= 15pF, TA = 25oC

• High-to-Low Voltage Level Converter for up to V

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . .–55

C to 125oC

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 5V

= 30%, NIH= 30%of VCCat

Pinout

CD54HC4049, CD54HC4050

(CERDIP)

CD74HC4049, CD74HC4050

(PDIP, SOIC, SOP, TSSOP)

TOP VIEW

4049 4050 4050 4049

1Y 1A 2Y 2A 3Y 3A

GND

1Y 1A 2Y 2A 3Y 3A

GND

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

NC 6Y 6A NC 5Y 5A 4Y 4A

= 16V

Description

The ’HC4049 and ’HC4050 are fabricated with high-speed silicon gate technology. They have a modiﬁed input protection structure that enables these parts to be usedas logic level translators which convert high-level logic to a lowlevel logic while operating off the low-level logic supply. For example, 15-V input pulse levels can be down-converted to 0-V to 5-V logic levels. The modiﬁed input protection structure protects the input from negative electrostatic discharge. These parts also can be used as simple buffers or inverters without level translation. The ’HC4049 and ’HC4050 are enhanced versions of equivalent CMOS types.

Ordering Information

TEMP. RANGE

PART NUMBER

CD54HC4049F3A –55 to 125 16 Ld CERDIP CD54HC4050F3A –55 to 125 16 Ld CERDIP CD74HC4049E –55 to 125 16 Ld PDIP CD74HC4049M –55 to 125 16 Ld SOIC CD74HCT4050MT –55 to 125 16 Ld SOIC CD74HC4049M96 –55 to 125 16 Ld SOIC CD74HC4049NSR –55 to 125 16 Ld SOP CD74HC4049PW –55 to 125 16 Ld TSSOP CD74HC4049PWR –55 to 125 16 Ld TSSOP CD74HC4049PWT –55 to 125 16 Ld TSSOP CD74HC4050E –55 to 125 16 Ld PDIP CD74HC4050M –55 to 125 16 Ld SOIC CD74HC4050MT –55 to 125 16 Ld SOIC CD74HC4050M96 –55 to 125 16 Ld SOIC

(oC) PACKAGE

CD74HC4050NSR –55 to 125 16 Ld SOP CD74HC4050PW –55 to 125 16 Ld TSSOP CD74HC4050PWR –55 to 125 16 Ld TSSOP CD74HC4050PWT –55 to 125 16 Ld TSSOP

NOTE: When ordering, use the entire part number. The sufﬁxes 96 and R denote tape and reel. The sufﬁx T denotes a small-quantity reel of 250.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright

CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050

Functional Diagram

Logic Diagrams

4050 4049 4049 4050

GND

HC4049 HC4050

A Y

CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . –0.5V to 7V

Input Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5V to 16V

DC Input Diode Current, I

For VI < –0.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–20mA

DC Output Diode Current, I

For VO < –0.5V or VO > VCC + 0.5V. . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

For VO > –0.5V or VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . .–55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input Voltage, VI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 15V

DC Output Voltage, VO. . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

Package Thermal Impedance, θJA(see Note 1):

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67oC/W

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73oC/W

NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W

PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W

Maximum Junction Temperature (Hermetic P ac kage or Die) . . . 175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . –65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

VOLTAGE RELATIONSHIPS MAXIMUM LIMITS

+16V

+7V

DC Electrical Speciﬁcations

PARAMETER SYMBOL

HC TYPES

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage CMOS Loads

High Level Output Voltage TTL Loads

Low Level Output Voltage CMOS Loads

Low Level Output Voltage TTL Loads

Input Leakage Current

TEST

CONDITIONS

25oC –40oC TO 85oC

(V)

–55oC TO

125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL–0.02 2 1.9 - - 1.9 - 1.9 - V

–0.02 4.5 4.4 - - 4.4 - 4.4 - V –0.02 6 5.9 - - 5.9 - 5.9 - V

–4 4.5 3.98 - - 3.84 - 3.7 - V

–5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

15 - 6 - - ±0.5 - ±5-±5

CD54HC4049, CD74HC4049, CD54HC4050, CD74HC4050

DC Electrical Speciﬁcations (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Quiescent Device Current

VCC or

GND

–55oC TO

25oC –40oC TO 85oC

(V)

125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

0 6 - - 2 - 20 - 40 µA

Switching Speciﬁcations Input t

, tf = 6ns

TEST

PARAMETER SYMBOL

CONDITIONS VCC(V)

HC TYPES

Propagation Delay, nA to nY HC4049 nA to nY HC4050

PLH,tPHL

CL= 50pF 2 - - 85 - 105 - 130 ns

4.5 - - 17 - 21 - 26 ns 6 - - 14 - 18 - 22 ns

CL= 15pF 5 - 6 - - - - - ns

Transition Times (Figure 1) t

TLH

, t

CL= 50pF 2 - - 75 - 95 - 110 ns

THL

4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns

Input Capacitance C Power Dissipation Capacitance

- - - - 10 - 10 - 10 pF

-5-35-----pF

(Notes 2, 3)

NOTES:

2. CPD is used to determine the dynamic power consumption, per gate.

3. PD = V

fi(CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

Test Circuit and Waveform

25oC

–40oC TO

85oC

–55oC TO

125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

tr = 6ns tf = 6ns

TLH

GND

INPUT

INVERTING

OUTPUT

THL

PHL

90% 50% 10%

90%

50%

10%

PLH

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

5962-8681901EA ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC

5962-8682001EA ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC CD54HC4049F3A ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC CD54HC4050F3A ACTIVE CDIP J 16 1 TBD Call TI Level-NC-NC-NC

CD74HC4049E ACTIVE PDIP N 16 25 Pb-Free

CD74HC4049M ACTIVE SOIC D 16 40 Green (RoHS &

CD74HC4049M96 ACTIVE SOIC D 16 2500 Green (RoHS &

CD74HC4049M96E4 ACTIVE SOIC D 16 2500 Green (RoHS &

CD74HC4049ME4 ACTIVE SOIC D 16 40 Green (RoHS &

CD74HC4049MT ACTIVE SOIC D 16 250 Green (RoHS &

CD74HC4049MTE4 ACTIVE SOIC D 16 250 Green (RoHS &

CD74HC4049NSR ACTIVE SO NS 16 2000 Green (RoHS &

CD74HC4049NSRE4 ACTIVE SO NS 16 2000 Green (RoHS &

CD74HC4049PW ACTIVE TSSOP PW 16 90 Green (RoHS &

CD74HC4049PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS &

CD74HC4049PWR ACTIVE TSSOP PW 16 2000 Green (RoHS &

CD74HC4049PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS &

CD74HC4049PWT ACTIVE TSSOP PW 16 250 Green (RoHS &

CD74HC4049PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS &

CD74HC4050E ACTIVE PDIP N 16 25 Pb-Free

CD74HC4050EE4 ACTIVE PDIP N 16 25 Pb-Free

CD74HC4050M ACTIVE SOIC D 16 40 Green (RoHS &

CD74HC4050M96 ACTIVE SOIC D 16 2500 Green (RoHS &

CD74HC4050M96E4 ACTIVE SOIC D 16 2500 Green (RoHS &

CD74HC4050ME4 ACTIVE SOIC D 16 40 Green (RoHS &

CD74HC4050MT ACTIVE SOIC D 16 250 Green (RoHS &

CD74HC4050MTE4 ACTIVE SOIC D 16 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

no Sb/Br)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-NC-NC-NC

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-NC-NC-NC

CU NIPDAU Level-1-260C-UNLIM

26-Sep-2005

(3)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

26-Sep-2005

(3)

no Sb/Br)

CD74HC4050NSR ACTIVE SO NS 16 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD74HC4050NSRE4 ACTIVE SO NS 16 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD74HC4050PW ACTIVE TSSOP PW 16 90 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD74HC4050PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD74HC4050PWR ACTIVE TSSOP PW 16 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD74HC4050PWRG4 ACTIVE TSSOP PW 16 2000 Green(RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD74HC4050PWT ACTIVE TSSOP PW 16 250 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD74HC4050PWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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Addendum-Page 2

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TEXAS INSTRUMENTS CD54HC4049 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual