Texas Instruments CD74HCT4046AE, CD74HCT4046AM96, CD74HCT4046AM, CD74HC4046APWR, CD74HC4046AM96 Datasheet
...
CD74HC4046A,
[ /Title
(CD74
HC404
6A,
CD74
HCT40
46A)
/Subject
(HighSpeed
CMOS
Data sheet acquired from Harris Semiconductor
SCHS204
February 1998
Features
• Operating Frequency Range
- Up to 18MHz (Typ) at V
- Minimum Center Frequency of 12MHz at V
• Choice of Three Phase Comparators
- EXCLUSIVE-OR
- Edge-Triggered JK Flip-Flop
- Edge-Triggered RS Flip-Flop
• Excellent VCO Frequency Linearity
• VCO-Inhibit Control for ON/OFF Keying and for Low
Standby Power Consumption
• Minimal Frequency Drift
• Operating Power Supply Voltage Range
- VCO Section . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 6V
- Digital Section . . . . . . . . . . . . . . . . . . . . . . . . 2V to 6V
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), VIH = 2V (Min)
IL
- CMOS Input Compatibility, I
= 5V
CC
o
= 30%, NIH = 30% of V
IL
≤ 1µA at VOL, V
l
C to 125oC
CC
OH
= 4.5V
CC
CD74HCT4046A
High-Speed CMOS Logic
Phase-Locked-Loop with VCO
Description
The Harris CD74HC4046A and CD74HCT4046A are highspeed silicon-gate CMOS devicesthat are pin compatible with
the CD4046B of the “4000B” series. They are specified in
compliance with JEDEC standard number 7.
The CD74HC4046A and CD74HCT4046A are phase-lockedloop circuits that contain a linear voltage-controlled oscillator
(VCO) and three different phase comparators (PC1, PC2 and
PC3). A signal input and a comparator input are common to
each comparator.
The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small
voltage signals. A self-bias input circuit keeps small voltage
signals within the linear region of the input amplifiers. With a
passive low-pass filter, the 4046A forms a second-order loop
PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques.
Ordering Information
TEMP.
PART NUMBER
CD74HC4046AE -55 to 125 16 Ld PDIP E16.3
CD74HCT4046AE -55 to 125 16 Ld PDIP E16.3
CD74HC4046AM -55 to 125 16 Ld SOIC M16.15
CD74HCT4046AM -55 to 125 16 Ld SOIC M16.15
NOTES:
1. When ordering, use the entire partnumber. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
RANGE (oC) PACKAGE
Applications
• FM Modulation and Demodulation
• Frequency Synthesis and Multiplication
• Frequency Discrimination
PKG.
NO.
• Tone Decoding
• Data Synchronization and Conditioning
• Voltage-to-Frequency Conversion
• Motor-Speed Control
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1998
1
File Number 1854.1
Pinout
Functional Diagram
CD74HC4046A, CD74HCT4046ACD74HC4046A, CD74HCT4046A
CD74HC4046A, CD74HCT4046A
(PDIP, SOIC)
TOP VIEW
16
PCP
PC1
COMP
VCO
COMP
SIG
OUT
OUT
OUT
INH
C1
C1
GND
IN
IN
1
2
3
IN
4
5
6
A
7
B
8
3
14
φ
V
CC
15
PC3
OUT
14
SIG
IN
13
PC2
OUT
12
R
2
11
R
1
10
DEM
OUT
9
VCO
IN
2
PC1
PC3
PC2
PCP
OUT
OUT
OUT
OUT
15
13
1
6
C1
A
VCO
C1
INH
7
B
11
R
1
12
R
2
IN
VCO
9
5
4
VCO
OUT
10
DEM
OUT
Pin Descriptions
PIN NUMBER SYMBOL NAME AND FUNCTION
1 PCP
2 PC1
3 COMP
4 VCO
OUT
OUT
IN
OUT
5 INH Inhibit Input
6C1
7C1
A
B
8 GND Ground (0V)
9 VCO
10 DEM
11 R
12 R
13 PC2
14 SIG
15 PC3
16 V
IN
OUT
1
2
OUT
IN
OUT
CC
Phase Comparator Pulse Output
Phase Comparator 1 Output
Comparator Input
VCO Output
Capacitor C1 Connection A
Capacitor C1 Connection B
VCO Input
Demodulator Output
Resistor R1 Connection
Resistor R2 Connection
Phase Comparator 2 Output
Signal Input
Phase Comparator 3 Output
Positive Supply Voltage
2
R2
R1
R5
CD74HC4046A, CD74HCT4046ACD74HC4046A, CD74HCT4046A
C1
674314
C1
C1
V
REF
R2
12
+
-
R1
11
10
DEM
OUT
-
+
B
A
VCO
-
+
INH
59
VCO
COMP
OUT
VCO
IN
SIG
IN
IN
PC1
OUT
2
PC2
PC3
OUT
PCP
OUT
V
CC
GND
p
n
OUT
15
13
1
R3
C2
S
D
Q
Q
R
D
CC
V
V
CC
D
CP
D
CP
UP
Q
Q
R
D
Q
DOWN
Q
R
D
FIGURE 1. LOGIC DIAGRAM
General Description
VCO
The VCO requires one external capacitor C1 (between C1
and C1B) and one external resistor R1 (between R1and
GND) or two external resistors R1 and R2 (between R
GND, and R
and GND). Resistor R1 and capacitor C1
2
determine the frequency range of the VCO. Resistor R2
enables the VCO to have a frequency offset if required. See
logic diagram, Figure 1.
The high input impedance of the VCO simplifies the design
of low-pass filters by giving the designer a wide choice of
resistor/capacitor ranges. In order not to load the low-pass
filter, a demodulator output of the VCO input voltage is provided at pin 10 (DEM
niques where the DEM
lower than the VCO input voltage, here the DEM
equals that of the VCO input. If DEM
resistor (R
unused, DEM
(VCO
input (COMP
) should be connected from DEM
S
OUT
) can be connected directly to the comparator
OUT
), or connected via a frequency-divider. The
IN
). In contrast to conventional tech-
OUT
voltage is one threshold voltage
OUT
OUT
is used, a load
OUT
OUT
should be left open. The VCO output
VCO output signal has a guaranteed duty factor of 50%. A
LOW level at the inhibit input (INH) enables the VCO and
demodulator, while a HIGH level turns both off to minimize
standby power consumption.
and
1
voltage
to GND; if
Phase Comparators
The signal input (SIG
A
) can be directly coupled to the self-
IN
biasing amplifier at pin 14, provided that the signal swing is
between the standard HC family input logic levels. Capacitive coupling is required for signals with smaller swings.
Phase Comparator 1 (PC1)
This is an Exclusive-OR network. The signal and comparator
input frequencies (f
) must have a 50% duty factor to obtain
i
the maximum locking range. The transfer characteristic of
PC1, assuming ripple (f
V
DEMOUT
=(VCC/π)(φSIGIN- φCOMPIN) where V
is the demodulator output at pin 10; V
= 2fi) is suppressed, is:
r
DEMOUT=VPC1OUT
(via low-pass filter).
The average output voltage from PC1, fed to the VCO input
via the low-pass filter and seen at the demodulator output at
pin 10 (V
DEMOUT
of signals (SIG
shown in Figure 2. The average of V
), is the resultant of the phase differences
) and the comparator input (COMPIN)as
IN
is equal to 1/2 V
DEM
when there is no signal or noise at SIGIN, and with this input
the VCO oscillates at the center frequency (f
forms for the PC1 loop locked at f
are shown in Figure 3.
o
). Typical wave-
o
DEMOUT
CC
3
CD74HC4046A, CD74HCT4046ACD74HC4046A, CD74HCT4046A
The frequency capture range (2f
) is defined as the fre-
C
quency range of input signals on which the PLL will lock if it
was initially out-of-lock. The frequency lock range (2f
)is
L
defined as the frequency range of input signals on which the
loop will stay locked if it was initially in lock. The capture
range is smaller or equal to the lock range.
With PC1, the capture range depends on the low-pass filter
characteristics and can be made as large as the lock range.
This configuration retains lock behavior even with very noisy
input signals. Typical of this type of phase comparator is that
it can lock to input frequencies close to the harmonics of the
VCO center frequency.
V
CC
V
DEMOUT (AV)
1/2 V
CC
0
o
0
o
φ
90
DEMOUT
180
o
FIGURE 2. PHASE COMPARATOR1: AVERAGE OUTPUT
VOLTAGE vs INPUT PHASE DIFFERENCE:
SIG
COMP
VCO
PC1
VCO
OUT
OUT
IN
IN
IN
V
DEMOUT
PIN); φ
= V
DEMOUT
= (VCC/π) (φSIGIN - φCOM-
PC1OUT
=(φSIGIN - φCOMPIN)
V
CC
GND
FIGURE 3. TYPICAL WAVEFORMS FOR PLL USING PHASE
COMPARATOR 1, LOOP LOCKED AT f
o
Phase Comparator 2 (PC2)
This is a positive edge-triggered phase and frequency detector. When the PLL is using this comparator, the loop is controlled by positive signal transitions and the duty factors of
SIG
and COMPINare not important. PC2 comprises two
IN
D-type flip-flops, control-gating and a three-state output
stage. The circuit functions as an up-down counter (Figure
1) where SIG
count. The transfer function of PC2, assuming ripple (f
causes an up-count and COMPINa down-
IN
r=fi
is suppressed, is:
V
DEMOUT
MOUT
V
PC2OUT
=(VCC/4π)(φSIGIN- φCOMPIN) where V
is the demodulator output at pin 10; V
(via low-pass filter).
DEMOUT
The average output voltage from PC2, fed to the VCO via the
low-pass filter and seen at the demodulator output at pin 10
(V
DEMOUT
SIG
for the PC2 loop locked at f
V
DEMOUT (AV)
FIGURE 4. PHASE COMPARATOR 2: AVERAGE OUTPUT
FIGURE 5. TYPICAL WAVEFORMS FOR PLL USING PHASE
When the frequencies of SIG
the phase of SIG
driver at PC2
the phase difference (φ
), is the resultant of the phase differences of
and COMPINas shown in Figure 4. Typical waveforms
IN
COMP
VCO
PC2
PCP
V
CC
1/2 V
CC
0
o
-360
VOLTAGE vs INPUT PHASE DIFFERENCE:
V
DEMOUT
PIN); φ
DEMOUT
SIG
IN
IN
OUT
OUT
HIGH IMPEDANCE OFF - STATE
VCO
IN
OUT
COMPARATOR 2, LOOP LOCKED AT f
leads that of COMPIN, the p-type output
IN
is held “ON” for a time corresponding to
OUT
are shown in Figure 5.
o
0
= V
= (VCC/4π) (φSIGIN - φCOM-
PC2OUT
=(φSIGIN - φCOMPIN)
and COMPINare equal but
IN
DEMOUT
). When the phase of SIG
o
φ
DEMOUT
o
lags that of COMPIN, the n-type driver is held “ON”.
When the frequency of SIG
is higher than that of COMPIN,
IN
the p-type output driver is held “ON” for most of the input signal cycle time, and for the remainder of the cycle both n- and
p-type drivers are “OFF” (three-state). If the SIG
is lower than the COMP
frequency, then it is the n-type
IN
frequency
IN
driver that is held “ON” for most of the cycle. Subsequently,
the voltage at the capacitor (C2) of the low-pass filter connected to PC2
)
inputs are equal in both phase and frequency. At this stable
varies until the signal and comparator
OUT
V
CC
GND
360
DE-
=
o
IN
4
CD74HC4046A, CD74HCT4046A
point the voltage on C2 remains constant as the PC2 output
is in three-state and the VCO input at pin 9 is a high impedance. Also in this condition, the signal at the phase comparator pulse output (PCP
used for indicating a locked condition.
Thus, for PC2, no phase difference exists between SIG
and COMPINover the full frequency range of the VCO.
Moreover, the power dissipation due to the low-pass filter is
reduced because both p- and n-type drivers are “OFF” for
most of the signal input cycle. It should be noted that the
PLL lock range for this type of phase comparator is equal to
the capture range and is independent of the low-pass filter.
With no signal present at SIG
to its lowest frequency.
) is a HIGH level and so can be
OUT
, the VCO adjusts, via PC2,
IN
IN
V
DEMOUT (AV)
1/2 V
V
CC
CC
0
o
0
180
o
φ
DEMOUT
360
o
Phase Comparator 3 (PC3)
This is a positive edge-triggered sequential phase detector using an RS-type flip-flop. When the PLL is using this
comparator, the loop is controlled by positive signal transitions and the duty factors of SIG
and COMPINare not
IN
important. The transfer characteristic of PC3, assuming
ripple (f
V
MOUT
V
= fi) is suppressed, is:
r
DEMOUT
=(VCC/2p) (fSIGIN- fCOMPIN) where V
is the demodulator output at pin 10; V
PC3OUT
(via low-pass filter).
DE-
DEMOUT
The average output from PC3, fed to the VCO via the lowpass filter and seen at the demodulator at pin 10 (V
), is the resultant of the phase differences of SIG
MOUT
DE-
IN
and COMPINas shown in Figure 6. Typical waveforms for
the PC3 loop locked at f
are shown in Figure 7.
o
The phase-to-output response characteristic of PC3 (Figure
6) differs from that of PC2 in that the phase angle between
SIG
and COMPINvaries between 0oand 360oand is 180
IN
at the center frequency. Also PC3 gives a greater voltage
swing than PC2 for input phase differences but as a consequence the ripple content of the VCO input signal is higher.
With no signal present at SIG
, the VCO adjusts, via PC3,
IN
to its highest frequency.
The only difference between the HC and HCT versions is the
input level specification of the INH input. This input disables
the VCO section. The comparator’s sections are identical, so
that there is no difference in the SIG
(pin 14) or COMP
IN
IN
(pin 3) inputs between the HC and the HCT versions.
FIGURE 6. PHASE COMPARATOR3: AVERAGE OUTPUT
VOLTAGE vs INPUT PHASE DIFFERENCE:
V
DEMOUT
PIN); φ
=
o
SIG
IN
COMP
IN
VCO
OUT
PC3
OUT
VCO
IN
FIGURE 7. TYPICAL WAVEFORMS FOR PLL USING PHASE
COMPARATOR 3, LOOP LOCKED AT f
= V
DEMOUT
= (VCC/2π) (φSIGIN - φCOM-
PC3OUT
= (φSIGIN - φCOMPIN)
V
CC
GND
o
5
CD74HC4046A, CD74HCT4046ACD74HC4046A, CD74HCT4046A
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, I
O
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Source or Sink Current per Output Pin, I
O
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, V
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
CC
Thermal Resistance (Typical, Note 3) θJA (oC/W)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CC
DC Electrical Specifications
PARAMETER SYMBOL
HC TYPES
VCO SECTION
INH High Level Input
Voltage
INH Low Level Input
Voltage
VCO
High Level
OUT
Output Voltage
CMOS Loads
VCO
High Level
OUT
Output Voltage
TTL Loads
VCO
OUT
Low Level
Output Voltage
CMOS Loads
VCO
OUT
Low Level
Output Voltage
TTL Loads
C1A, C1B Low Level
Output Voltage
(Test Purposes Only)
V
IH
V
IL
V
OH
V
OL
V
OL
TEST
CONDITIONS
V
CC
(V)
25oC -40oC TO 85oC -55oCTO125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
- - 3 2.1 - - 2.1 - 2.1 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
- - 3 - - 0.9 - 0.9 - 0.9 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
VIHor VIL-0.02 3 2.9 - - 2.9 - 2.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
- - ---- - - - V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
- - ---- - - - V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
VILor V
4 4.5 - - 0.40 - 0.47 - 0.54 V
IH
5.2 6 - - 0.40 - 0.47 - 0.54 V
6
CD74HC4046A, CD74HCT4046A
DC Electrical Specifications (Continued)
TEST
PARAMETER SYMBOL
INH VCOIN Input
Leakage Current
CONDITIONS
I
VCC or
I
GND
V
CC
(V)
-6--±0.1 - ±1-±1µA
R1 Range (Note 4) - - - 4.5 3 - 300 - - - - kΩ
R2 Range (Note 4) - - - 4.5 3 - 300 - - - - kΩ
C1 Capacitance
Range
---3--No
4.5 - - - - - - pF
6-- ----pF
VCOIN Operating
Voltage Range
- Over the range
specified for R1 for
LinearitySeeFigure
10, and 35 - 38
3 1.1 - 1.9 - - - - V
4.5 1.1 - 3.2 - - - - V
6 1.1 - 4.6 - - - - V
(Note 5)
PHASE COMPARATOR SECTION
SIGIN, COMP
IN
DC Coupled
High-Level Input
Voltage
SIGIN, COMP
IN
DC Coupled
Low-Level Input
Voltage
PCP
, PCn OUT
OUT
High-Level Output
Voltage
CMOS Loads
PCP
, PCn OUT
OUT
High-Level Output
Voltage
V
IH
- - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
V
IL
- - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
V
VILor VIH-0.02 2 1.9 - - 1.9 - 1.9 - V
OH
4.5 4.4 - - 4.4 - 4.4 - V
6 5.9 - - 5.9 - 5.9 - V
V
OH
VILor V
-4 4.5 3.98 - - 3.84 - 3.7 - V
IH
-5.2 6 5.48 - - 5.34 - 5.2 - V
TTL Loads
PCP
Low-Level Output
Voltage
CMOS Loads
PCP
Low-Level Output
Voltage
, PCn OUT
OUT
, PCn OUT
OUT
V
VILor VIH0.02 2 - - 0.1 - 0.1 - 0.1 V
OL
4.5 - - 0.1 - 0.1 - 0.1 V
6 - - 0.1 - 0.1 - 0.1 V
V
OL
VILor V
4 4.5 - - 0.26 - 0.33 - 0.4 V
IH
5.2 6 - - 0.26 - 0.33 - 0.4 V
TTL Loads
SIGIN, COMPINInput
Leakage Current
I
VCC or
I
GND
-2--±3-±4-±5µA
3--±7-±9-±11 µA
4.5 - - ±18 - ±23 - ±29 µA
6--±30 - ±38 - ±45 µA
PC2
Three-State
OUT
I
OZ
VILor V
-6--±0.5 - ±5-±10 µA
IH
Off-State Current
SIGIN, COMPINInput
Resistance
R
I
VI at Self-Bias
Operation Point:
∆VI, 0.5V,
See Figure 10
3 - 800 - - - - - kΩ
4.5 - 250 - - - - - kΩ
6 - 150 - - - - - kΩ
DEMODULATOR SECTION
Resistor Range R
S
at RS > 300kΩ
Leakage Current
Can Influence
V
DEMOUT
3 50 - 300 - - - - kΩ
4.5 50 - 300 - - - - kΩ
6 50 - 300 - - - - kΩ
25oC -40oC TO 85oC -55oCTO125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
----pF
Limit
7
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