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CD54HC4020F
Datasheet
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Texas Instruments CD74HCT4020E, CD74HCT4020M96, CD74HCT4020M, CD74HC4020M96, CD74HC4020M Datasheet

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CD74HC4020,
/ j
[ /Title (CD74 HC402 0, CD74 HCT40
20) Sub­ect
(High Speed CMOS
Data sheet acquired from Harris Semiconductor SCHS201
February 1998
Features
• Fully Static Operation
• Buffered Inputs
• Common Reset
• Negative Edge Clocking
= 25oC
A
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
= 60 MHz at VCC = 5V, CL = 15pF,
MAX
= 30%, NIH = 30% of V
IL
o
C to 125oC
CC
CD74HCT4020
High Speed CMOS Logic 14-Stage Binary Counter
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, V
= 0.8V (Max), VIH = 2V (Min)
IL
- CMOS Input Compatibility, I
Description
The Harris CD74HC4020 and CD74HCT4020 are 14-stage ripple-carry binary counters. All counter stages are master­slave flip-flops. The state of the stage advances one count on the negative clock transition of each input pulse; a high voltage level on the MR line resets all counters to their zero state. All inputs and outputs are buffered.
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE
CD74HC4020E -55 to 125 16 Ld PDIP E16.3 CD74HCT4020E -55 to 125 16 Ld PDIP E16.3
≤ 1µA at VOL, V
l
OH
PKG.
NO.
Pinout
CD74HC4020, CD74HCT4020
(PDIP, SOIC)
TOP VIEW
16
Q Q Q
Q6 Q Q Q
GND
1
12
2
13
3
14
4 5
5
6
7
7
4
8
V Q
15 14
Q
13
Q
12
Q
11
MR
10
CP Q
9
CC
11 10 8 9
‘
1
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© Harris Corporation 1998
1
File Number 1484.2
Functional Diagram
CD74HC4020, CD74HCT4020
V
CC
16
10
INPUT
PULSES
14-STAGE
RIPPLE
COUNTER
11
MASTER
RESET
GND
9
Q1’
7
Q4
5
Q5
4
Q6
6
Q7
13
Q8
12
Q9
14
Q10
15
Q11
1
Q12
2
Q13
3
Q14
8
TRUTH TABLE
BUFFERED OUTPUTS
CP COUNT MR OUTPUT STATE
↑ L No Change ↓ L Advance to Next State
X H All Outputs Are Low
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, ↑ = Transition from Low to High Level, ↓ = Transition from High to Low.
2
Logic Diagram
CD74HC4020, CD74HCT4020
3
Q
R
14
CP Q
CP
Q
R
13
CP Q
CP
Q
R
12
CP Q
CP
Q
R
11
CP Q
CP
Q
R
10
CP Q
CP
Q
9
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
R
CP
Q
8
R
CP
Q
7
R
CP
Q
6
R
CP
Q
5
R
CP
Q
4
R
CP
2
1
15
14
12
13
6
4
5
7
14
Q
13
Q
12
Q
11
Q
10
Q
9
Q
8
Q
7
Q
6
Q
5
Q
4
Q
Q
3
CP Q
CP Q
CP Q
10
CP
R
CP
Q
2
R
CP
Q
Q’ I
R
CP
11
MR
9
’
1
Q
3
CD74HC4020, CD74HCT4020
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, I
O
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, I
CC orIGND
. . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, V
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
CC
Thermal Resistance (Typical, Note 3) θJA (oC/W)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CC
DC Electrical Specifications
PARAMETER SYMBOL
HC TYPES
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage CMOS Loads
High Level Output Voltage TTL Loads
Low Level Output Voltage CMOS Loads
Low Level Output Voltage TTL Loads
Input Leakage Current
Quiescent Device Current
V
IH
V
IL
V
OH
V
OL
I
I
I
CC
TEST
CONDITIONS
(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
I
V
CC
(V)
o
C -40oC TO 85oC -55oCTO125oC
25
UNITSV
- - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V
- - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V
VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
- - ---- - - - V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
- - ---- - - - V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
VCC or
-6--±0.1 - ±1-±1µA
GND
VCC or
0 6 - - 8 - 80 - 160 µA
GND
4
CD74HC4020, CD74HCT4020
DC Electrical Specifications (Continued)
TEST
CONDITIONS
PARAMETER SYMBOL
HCT TYPES
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
V
IH
V
IL
V
OH
CMOS Loads High Level Output
Voltage TTL Loads
Low Level Output Voltage
V
OL
CMOS Loads Low Level Output
Voltage TTL Loads
Input Leakage Current
Quiescent Device Current
Additional Quiescent Device Current Per
I
I
I
CC
∆I
CC
Input Pin: 1 Unit Load
NOTE: For dual-supply systems theoretical worst case (V
(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
I
- - 4.5 to
- - 4.5 to
VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-4 4.5 3.98 - - 3.84 - 3.7 - V
VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V
4 4.5 - - 0.26 - 0.33 - 0.4 V
VCCand
0 5.5 - - ±0.1 - ±1-±1µA
GND
VCC or
0 5.5 - - 8 - 80 - 160 µA
GND
V
CC
- 4.5 to
-2.1
o
C -40oC TO 85oC -55oCTO125oC
V
CC
25
(V)
2--2- 2 - V
5.5
- - 0.8 - 0.8 - 0.8 V
5.5
- 100 360 - 450 - 490 µA
5.5
= 2.4V, VCC = 5.5V) specification is 1.8mA.
I
UNITSV
HCT Input Loading Table
INPUT UNIT LOADS
MR 0.65 CP 0.5
NOTE: Unit Load is ∆ICClimit specified in DC Electrical Table, e.g., 360µA max at 25oC.
Prerequisite for Switching Specifications
PARAMETER SYMBOL VCC (V)
HC TYPES
Maximum Input Pulse Frequency
Input Pulse Width t
Reset Removal Time t
f
MAX
W
REM
26-5-4-ns
4.530-25-20-ns 635-29-24-ns 2 80 - 100 - 120 - ns
4.516-20-24-ns 614-17-20-ns 250-65-75-ns
4.510-13-15-ns 6 9 -11-13-ns
o
25
C -40oC TO 85oC -55oC TO 125oC
UNITSMIN MAX MIN MAX MIN MAX
5
CD74HC4020, CD74HCT4020
Prerequisite for Switching Specifications (Continued)
25
PARAMETER SYMBOL V
Reset Pulse Width t
HCT TYPES
Maximum Input Pulse Frequency
Input Pulse Width t Reset Recovery Time t Reset Pulse Width t
f
MAX
REC
W
W
W
(V)
CC
2 80 - 100 - 120 - ns
4.516-20-24-ns 614-17-20-ns
4.5 25 - 20 - 16 - MHz
4.520-25-30-ns
4.510-13-15-ns
4.520-25-30-ns
o
C -40oC TO 85oC -55oC TO 125oC
UNITSMIN MAX MIN MAX MIN MAX
Switching Specifications Input t
PARAMETER SYMBOL
, tf = 6ns
r
TEST
CONDITIONS
V
CC
25oC -40oC TO 85oC -55oC TO 125oC
(V)
HC TYPES
Propagation Delay Time (Figure 1)
t
PLH,
t
PHL
CL= 50pF 2 - - 140 - 175 - 210 ns
CP to Q1’ Output 4.5 - - 28 - 35 - 42 ns
CL=15pF 5 - 11 - - - - - ns CL= 50pF 6 - - 24 - 30 - 36 ns
Qnto Qn+ 1 t
t
CL= 50pF 2 - - 75 - 95 - 110 ns
PLH, PHL
4.5 - - 15 - 19 - 22 ns CL=15pF 5 - 6 - - - - - ns CL= 50pF 6 - - 13 - 16 - 19 ns
MR to Q
n
t
PLH,
t
PHL
CL= 50pF 2 - - 170 - 215 - 255 ns
4.5 - - 34 - 43 - 51 ns
5 - 14 - - - - - ns 6 - - 29 - 37 - 43 ns
Output Transition Time (Figure 1)
t
TLH,tTHLCL
= 50pF 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns Input Capacitance C Power Dissipation Capaci-
C
CL= 50pF - - - 10 - 10 - 10 pF
IN
CL=15pF 5 - 30 - - - - - pF
PD
tance (Notes 4, 5)
HCT TYPES
Propagation Delay Time (Figure 2)
t
PLH,
t
PHL
CL= 50pF 4.5 - - 40 - 50 - 60 ns
CP to Q1’ Output CL=15pF 5 - 17 - - - - - ns Qnto Qn+ 1 t
MR to Q
n
t
t
t
CL= 50pF 4.5 - - 15 - 19 - 22 ns
PLH, PHL
CL=15pF 5 - 6 - - - - - ns CL= 50pF 4.5 - - 40 - 50 - 60 ns
PLH, PHL
CL=15pF 5 - 17 - - - - - ns
UNITSMIN TYP MAX MIN MAX MIN MAX
6
CD74HC4020, CD74HCT4020
Switching Specifications Input t
PARAMETER SYMBOL
Output Transition t Input Capacitance C Power Dissipation Capaci-
, tf = 6ns (Continued)
r
CONDITIONS
TLH,tTHLCL
CL=15pF - - - 10 - 10 - 10 pF
IN
C
CL=15pF 5 - 30 - - - - - pF
PD
TEST
V
CC
(V)
= 50pF 4.5 - - 15 - 19 - 22 ns
tance (Notes 4, 5)
NOTES:
4. CPD is used to determine the dynamic power consumption, per package.
5. PD = V
2
fi(CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
CC
Test Circuits and Waveforms
trC
L
CLOCK
10%
90%
50%
10%
tfC
t
L
WL
tWL+ tWH=
50%
t
WH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table.For f
, input duty cycle = 50%.
MAX
FIGURE 1. HC CLOCK PULSE RISE AND FALLTIMES AND
PULSE WIDTH
f
CL
50%
I
V
CC
GND
NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table.For f
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
t
rCL
CLOCK
= 6ns
0.3V
2.7V
1.3V
0.3V
t
t
fCL
WL
= 6ns
+ tWH=
t
WL
1.3V
t
WH
, input duty cycle = 50%.
MAX
I
fC
3V
1.3V GND
FIGURE 2. HCT CLOCK PULSE RISE AND FALLTIMES AND
PULSE WIDTH
L
7
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