Texas Instruments CD54HC4017F3A Datasheet
OUTPUT STATE
†
CD54HC4017
DECADE COUNTER/DIVIDER
WITH TEN DECODED OUTPUTS
SGDS011 – MAY 1999
GND
F PACKAGE
(TOP VIEW)
5
1
1
2
0
3
2
4
5
6
6
7
7
3
8
16
15
14
13
12
11
10
V
CC
MR
CP
CE
TC
9
4
9
8
D
2-V to 6-V Operation
D
Fully Static Operation
D
Buffered Inputs
D
Common Reset
D
Positive-Edge Clocking
D
Balanced Propagation Delay and Transition
Times
D
High Noise Immunity: NIL = 30%, NIH = 30%
of VCC at VCC = 5 V
D
Packaged in Ceramic (F) DIP Package and
Also Available in Chip Form (H)
description
The CD54HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each
decoded output normally is low and sequentially goes high on the low-to-high transition of the clock (CP) input.
Each output stays high for one clock period of the ten-clock-period cycle. The terminal count (TC) output
transitions low to high after output ten (9) goes low, and can be used in conjunction with the clock enable (CE)
input to cascade several stages. CE disables counting when in the high state. The master reset (MR) input, when
taken high, sets all the decoded outputs, except 0, to low.
The CD54HC4017 is characterized for operation over the full military temperature range of –55°C to 125°C.
FUNCTION TABLE
INPUTS
CP CE MR
L X L No change
X H L No change
X XH
↑ L L Increments counter
↓ X L No change
X ↑ L No change
H ↓ L Increments counter
†
If n < 5, TC = H; otherwise, TC = L.
0 = H
1–9 = L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
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CD54HC4017
DECADE COUNTER/DIVIDER
WITH TEN DECODED OUTPUTS
SGDS011 – MAY 1999
logic diagram (positive logic)
10
11
12
3
0
2
1
4
2
7
3
4
1
5
5
6
6
9
Decoded Decimal Out
7
8
9
TC
2
MR
CE
CP
15
13
14
D
Q
C
Q
R
D
Q
C
Q
R
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Q
C
Q
R
D
Q
C
Q
R
D
Q
C
Q
R
PARAMETER
TEST CONDITIONS
V
MIN
MAX
UNIT
TTL loads
V
V
V
TTL loads
V
V
or V
CD54HC4017
DECADE COUNTER/DIVIDER
WITH TEN DECODED OUTPUTS
SGDS011 – MAY 1999
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
†
Input clamp current, IIK (VI < 0 V or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 V or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, each output pin, IO (VO > –0.5 V or VO < VCC + 0.5 V) ±25 mA. . . . . . . . . . . . . .
VCC or ground current, ICC ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating (see Note 1)
MIN MAX UNIT
V
V
V
V
V
t
t
T
NOTE 1: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to TI application report
Supply voltage 2 6 V
CC
VCC = 2 V 1.5
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
Input transition (rise and fall) time
Operating free-air temperature –55 125 °C
A
of Slow or Floating CMOS Inputs
, literature number SCBA004.
VCC = 4.5 V
VCC = 6 V 4.2
VCC = 2 V 0 0.5
VCC = 4.5 V
VCC = 6 V 0 1.8
VCC = 2 V 0 1000
VCC = 4.5 V
VCC = 6 V 0 400
3.15
0 1.35
CC
CC
0 500
V
V
V
V
ns
Implications
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C
MIN MAX
4.4 4.4
V
0.1 0.1
V
V
V
I
I
C
OH
OL
I
CC
CMOS loads VI = VIH or VIL, IOH = –0.02 mA
=
or
I
IH
IL
CMOS loads VI = VIH or VIL, IOL = 0.02 mA
=
I
IH
IL
VI = VCC or 0 6 V ±100 ±1000 nA
VI = VCC or 0, IO = 0 6 V 8 160 µA
i
CC
2 V 1.9 1.9
4.5 V
6 V 5.9 5.9
IOH = –4 mA 4.5 V 3.98 3.7
IOH = –5.2 mA 6 V 5.48 5.2
2 V 0.1 0.1
4.5 V
6 V 0.1 0.1
IOL = 4 mA 4.5 V 0.26 0.4
IOL = 5.2 mA 6 V 0.26 0.4
2 V to 6 V 10 10 pF
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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