Texas Instruments CD74HC4002PWR, CD74HC4002M96, CD74HC4002M, CD74HC4002E, CD54HC4002F3A Datasheet

Data sheet acquired from Harris Semiconductor

/

SCHS197

August 1997

CD74HC4002

High Speed CMOS Logic

Dual 4-Input NOR Gate

[ /Title
(CD74H
C4002)

Subject
(High
Speed
CMOS
Logic
Dual 4­Input
NOR
Gate)

Features

• Typical Propagation Delay = 8ns at VCC = 5V,
C

= 15pF, TA = 25oC

L

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

o

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High NoiseImmunity: N

V

= 5V

CC

= 30%, NIH= 30%of VCCat

IL

C to 125oC

Pinout

Description

The CD74HC4002 logic gate utilizes silicon gate CMOS
technology to achieve operating speeds similar to LSTTL
gates with the low power consumption of standard CMOS
integrated circuits. All devices have the ability to drive 10
LSTTL loads. The CD74HC4002 logic family is functional as
well as pin compatible with the standard 74LS logic family.

Ordering Information

PART NUMBER TEMP. RANGE (oC) PACKAGE

CD74HC4002E -55 to 125 14 Ld PDIP E14.3
CD74HC4002M -55 to 125 14 Ld SOIC M14.15

NOTES:

1. When ordering, use the entire part number.Add the suffix 96 to

2. Die for this part number is available which meets all electrical

CD74HC4002

(PDIP, SOIC)

TOP VIEW

PKG.

NO.

obtain the variant in the tape and reel.

specifications. Please contact your local sales office or Harris
customer service for ordering information.

1Y

1
2

1A

3

1B

4

1C

5

1D

6

NC

7

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

14

V

CC

2Y

13
12

2D

11

2C

10

2B

9

2A

8

NC

1

File Number 1776.1

Functional Diagram

CD74HC4002

2

1A

3

1B

4

1C

5

1D

9

2A

10

2B

11

2C

12

2D

TRUTH TABLE

INPUTS OUTPUT

nA nB nC nD nY

LLLLH

1

1Y

13

2Y

GND = 7

= 14

V

CC

NC = 6, 8

Logic Symbol

HXXXL
XHXXL
XXHXL
XXXHL

NOTE: H= High VoltageLevel,L = LowVoltageLevel,X = Irrelevant

nA
nB

nY

nC
nD

2