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Data sheet acquired from Harris Semiconductor
SCHS184C
September 1997 - Revised February 2004
CD54HC377, CD74HC377,
CD54HCT377, CD74HCT377
High-Speed CMOS Logic
Octal D-Type Flip-Flop With Data Enable
/Title
CD74
C377
D74
CT37
)
Subect
High
peed
MOS
ogic
ctal
-
ype
lip-
Features
• Buffered Common Clock
• Buffered Inputs
• Typical Propagation Delay at C
V
= 5V, TA = 25oC
CC
- 14 ns (HC Types
- 16 ns (HCT Types)
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High NoiseImmunity: N
V
= 5V
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), VIH = 2V (Min)
IL
- CMOS Input Compatibility, I
= 15pF,
L
o
C to 125oC
= 30%, NIH= 30%of VCCat
IL
≤ 1µA at VOL, V
l
OH
Description
The ’HC377 and ’HCT377 are octal D-type flip-flops with a
buffered clock (CP) common to all eight flip-flops. All the flipflops are loaded simultaneously on the positive edge of the
clock (CP) when the Data Enable (
E) is Low.
Ordering Information
TEMP. RANGE
PART NUMBER
CD54HC377F3A -55 to 125 20 Ld CERDIP
CD54HCT377F3A -55 to 125 20 Ld CERDIP
CD74HC377E -55 to 125 20 Ld PDIP
CD74HC377M -55 to 125 20 Ld SOIC
CD74HC377M96 -55 to 125 20 Ld SOIC
CD74HC377PW -55 to 125 20 Ld TSSOP
CD74HC377PWR -55 to 125 20 Ld TSSOP
CD74HCT377E -55 to 125 20 Ld PDIP
CD74HCT377M -55 to 125 20 Ld SOIC
CD74HCT377M96 -55 to 125 20 Ld SOIC
NOTE: Whenordering, use the entire part number. The suffixes
96 and R denote tape and reel.
(oC) PACKAGE
Pinout
CD54HC377, CD54HCT377
(CERDIP)
CD74HC377
(PDIP, SOIC, TSSOP)
CD74HCT377
(PDIP, SOIC)
TOP VIEW
1
E
Q
2
0
D
3
0
D
4
1
Q
5
1
Q
6
2
D
7
2
8
D
3
9
Q
3
GND
10
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2004, Texas Instruments Incorporated
1
V
20
CC
Q
19
7
D
18
7
D
17
6
Q
16
6
Q
15
5
D
14
5
D
13
4
12
Q
4
11
CP
CD54HC377, CD74HC377, CD54HCT377, CD74HCT377
Functional Diagram
3
D
0
4
D
1
7
D
2
8
D
3
13
D
4
14
D
5
17
D
6
18
D
7
CP
E
11 1
2
Q
5
Q
6
Q
9
Q
12
Q
15
Q
16
Q
19
Q
GND = 10
= 20
V
CC
0
1
2
3
4
5
6
7
TRUTH TABLE
INPUTS OUPUTS
OPERATING MODE
CP EDnQ
n
Load “1” ↑ lh H
Load “0” ↑ ll L
Hold (Do Nothing) ↑ h X No Change
X H X No Change
H = High Voltage Level Steady State.
h = High Voltage Level One Set-up Time Prior to the Low to High Clock Transition.
L = Low Voltage Level Steady State.
l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition.
X = Don’t Care.
↑ = Low to High Clock Transition.
Logic Diagram
E
CP
D
0
CP
D
1
QD
Q
0
CP
D
2
QD
Q
1
CP
D
3
QD
Q
2
CP
D
4
QD
Q
3
CP
D
5
QD
Q
4
CP
D
6
QD
Q
5
CP
D
7
QD
Q
QD
CP
6
Q
7
2
CD54HC377, CD74HC377, CD54HCT377, CD74HCT377
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, I
O
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, I
CC orIGND
. . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, V
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
CC
Thermal Resistance (Typical, Note 1) θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 69
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 58
PW (TSSOP) Package. . . . . . . . . . . . . . . . . . . . . . . 83
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CC
DC Electrical Specifications
PARAMETER SYMBOL
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
V
IH
V
IL
V
OH
V
OL
I
I
I
CC
TEST
CONDITIONS
(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
I
V
CC
(V)
o
25
C -40oC TO 85oC -55oC TO 125oC
UNITSV
- - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
- - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
- - ---- - - - V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
- - ---- - - - V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
VCC or
-6--±0.1 - ±1-±1 µA
GND
VCC or
0 6 - - 8 - 80 - 160 µA
GND
3
CD54HC377, CD74HC377, CD54HCT377, CD74HCT377
DC Electrical Specifications (Continued)
TEST
CONDITIONS
PARAMETER SYMBOL
HCT TYPES
High Level Input
Voltage
Low Level Input
V
IH
V
IL
Voltage
High Level Output
Voltage
V
OH
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
V
OL
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
I
I
I
CC
∆I
CC
(Note 2)
Input Pin: 1 Unit Load
NOTE:
2. For dual-supply systems theoretical worst case (V
(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
I
- - 4.5 to
- - 4.5 to
VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V
VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V
VCCand
GND
VCC or
GND
V
CC
-2.1
o
C -40oC TO 85oC -55oC TO 125oC
V
CC
(V)
25
UNITSV
2--2- 2 - V
5.5
- - 0.8 - 0.8 - 0.8 V
5.5
-4 4.5 3.98 - - 3.84 - 3.7 - V
4 4.5 - - 0.26 - 0.33 - 0.4 V
0 5.5 - - ±0.1 - ±1-±1 µA
0 5.5 - - 8 - 80 - 160 µA
- 4.5 to
- 100 360 - 450 - 490 µA
5.5
= 2.4V, VCC = 5.5V) specification is 1.8mA.
I
HCT Input Loading Table
INPUT UNIT LOADS
E 1.5
CP 0.5
All Dn Inputs 0.25
NOTE: Unit Load is ∆ICClimit specified in DC Electrical Table,e.g.,
360µA max at 25oC.
Prerequisite for Switching Specifications
PARAMETER SYMBOL
HC TYPES
Maximum Clock
Frequency
Clock Pulse Width t
f
MAX
W
TEST
CONDITIONS
- 26--5-4-MHz
- 2 80 - - 100 - 120 - ns
V
CC
(V)
4.5 30 - - 25 - 20 - MHz
6 35 - - 29 - 23 - MHz
4.5 16 - - 20 - 24 - ns
614- -17-20-ns
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
4
CD54HC377, CD74HC377, CD54HCT377, CD74HCT377
Prerequisite for Switching Specifications (Continued)
PARAMETER SYMBOL
Set-up Time,
E, Data to CP
Hold Time,
Data to CP
Hold Time,
E to CP
HCT TYPES
Maximum Clock
Frequency
Clock Pulse Width t
Set-up, Time
E, Data to CP
Hold Time,
Data to CP
Hold Time,
E to CP
t
SU
t
t
f
MAX
t
SU
t
t
H
H
W
H
H
TEST
CONDITIONS
V
CC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
- 2 60 - - 75 - 90 - ns
4.5 12 - - 15 - 18 - ns
610- -13-15-ns
- 23--3-3-ns
4.53--3-3-ns
63--3-3-ns
- 25--5-5-ns
4.55--5-5-ns
65--5-5-ns
- 4.5 25 - - 20 - 16 - MHz
- 4.5 20 - - 25 - 30 - ns
- 4.5 12 - - 15 - 18 - ns
- 4.53--3-3-ns
- 4.55--5-5-ns
UNITSMIN TYP MAX MIN MAX MIN MAX
Switching Specifications Input t
, tf = 6ns
r
-40oC TO
PARAMETER SYMBOL
TEST
CONDITIONS
V
CC
25oC
(V)
85oC -55oC TO 125oC
HC TYPES
Propagation Delay (Figure 1) t
CP to Q 4.5 - - 35 - 44 - 53 ns
PLH,
t
PHL
CL= 50pF 2 - - 175 - 220 - 265 ns
CL=15pF 5 - 14 - - - - - ns
CL= 50pF 6 - - 30 - 37 - 45 ns
Output Transition Time
(Figure 1)
t
TLH,tTHLCL
= 50pF 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
Input Capacitance C
Maximum Clock Frequency f
Power Dissipation Capacitance
MAXCL
C
CL= 50pF - - - 10 - 10 - 10 pF
IN
=15pF 5 - 60 - - - - - MHz
CL=15pF 5 - 31 - - - - - pF
PD
(Notes 3, 4)
HCT TYPES
Propagation Delay (Figure 1) t
CP to Q CL=15pF 5 - 16 - - - - - ns
Output Transition Time
PLH,
t
PHL
t
TLH,tTHLCL
CL= 50pF 4.5 - - 38 - 48 - 57 ns
= 50pF 4.5 - - 15 - 19 - 22 ns
(Figure 1)
Input Capacitance C
CL= 50pF - - - 10 - 10 - 10 pF
IN
UNITSMIN TYP MAX MIN MAX MIN MAX
5
CD54HC377, CD74HC377, CD54HCT377, CD74HCT377
Switching Specifications Input t
PARAMETER SYMBOL
Maximum Clock Frequency f
Power Dissipation Capacitance
, tf = 6ns (Continued)
r
TEST
CONDITIONS
MAXCL
C
PD
=15pF 5 - 50 - - - - - MHz
CL=15pF 5 - 35 - - - - - pF
V
CC
(V)
(Notes 3, 4)
NOTES:
3. CPD is used to determine the dynamic power consumption, per flip-flop.
4. PD = V
2
fi(CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
CC
Test Circuits and Waveforms
tfC
L
50%
t
H(L)
t
SU(L)
V
CC
GND
V
CC
50%
GND
CLOCK
INPUT
DAT A
INPUT
t
SU(H)
trC
L
90%
10%
t
H(H)
CLOCK
INPUT
DAT A
INPUT
t
SU(H)
25oC
trC
-40oC TO
85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
1.3V
tfC
L
1.3V
t
H(L)
1.3V
t
SU(L)
3V
GND
3V
GND
L
2.7V
0.3V
t
H(H)
1.3V
OUTPUT
t
REM
V
CC
SET, RESET
OR PRESET
50%
90%
t
PLH
IC
t
TLH
C
L
50pF
90%
50%
10%
t
PHL
t
THL
GND
FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVALTIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
OUTPUT
t
REM
3V
SET, RESET
OR PRESET
1.3V
90%
1.3V
t
IC
t
PLH
TLH
C
L
50pF
90%
1.3V
10%
t
t
PHL
THL
GND
FIGURE 2. HCT SETUPTIMES, HOLDTIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
6
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
5962-8976901RA ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC
CD54HC377F3A ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC
CD54HCT377F3A ACTIVE CDIP J 20 1 TBD Call TI Level-NC-NC-NC
CD74HC377E ACTIVE PDIP N 20 20 Pb-Free
CD74HC377EE4 ACTIVE PDIP N 20 20 Pb-Free
CD74HC377M ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br)
CD74HC377M96 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br)
CD74HC377M96E4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br)
CD74HC377ME4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br)
CD74HC377PW ACTIVE TSSOP PW 20 70 Green (RoHS &
no Sb/Br)
CD74HC377PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS &
no Sb/Br)
CD74HC377PWR ACTIVE TSSOP PW 20 2000 Green (RoHS &
no Sb/Br)
CD74HC377PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS &
no Sb/Br)
CD74HCT377E ACTIVE PDIP N 20 20 Pb-Free
CD74HCT377EE4 ACTIVE PDIP N 20 20 Pb-Free
CD74HCT377M ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br)
CD74HCT377M96 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br)
CD74HCT377M96E4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br)
CD74HCT377ME4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-NC-NC-NC
CU NIPDAU Level-NC-NC-NC
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-NC-NC-NC
CU NIPDAU Level-NC-NC-NC
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
(3)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
26-Sep-2005
Addendum-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
1,20 MAX
14
0,30
0,19
8
4,50
4,30
PINS **
7
Seating Plane
0,15
0,05
8
1
A
DIM
14
0,10
6,60
6,20
M
0,10
0,15 NOM
0°–8°
2016
Gage Plane
24
0,25
0,75
0,50
28
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
4040064/F 01/97
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