TEXAS INSTRUMENTS CD54HC377 Technical data

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Data sheet acquired from Harris Semiconductor
SCHS184C

September 1997 - Revised February 2004

CD54HC377, CD74HC377,

CD54HCT377, CD74HCT377

High-Speed CMOS Logic

Octal D-Type Flip-Flop With Data Enable

/Title
CD74

C377

D74
CT37

)
Sub­ect
High

peed

MOS

ogic

ctal

-

ype

lip-

Features

• Buffered Common Clock

• Buffered Inputs

• Typical Propagation Delay at C
V

= 5V, TA = 25oC

CC

- 14 ns (HC Types

- 16 ns (HCT Types)

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High NoiseImmunity: N

V

= 5V

CC

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 15pF,

L

o

C to 125oC

= 30%, NIH= 30%of VCCat

IL

≤ 1µA at VOL, V

l

OH

Description

The ’HC377 and ’HCT377 are octal D-type flip-flops with a
buffered clock (CP) common to all eight flip-flops. All the flip­flops are loaded simultaneously on the positive edge of the
clock (CP) when the Data Enable (

E) is Low.

Ordering Information

TEMP. RANGE

PART NUMBER

CD54HC377F3A -55 to 125 20 Ld CERDIP
CD54HCT377F3A -55 to 125 20 Ld CERDIP
CD74HC377E -55 to 125 20 Ld PDIP
CD74HC377M -55 to 125 20 Ld SOIC
CD74HC377M96 -55 to 125 20 Ld SOIC
CD74HC377PW -55 to 125 20 Ld TSSOP
CD74HC377PWR -55 to 125 20 Ld TSSOP
CD74HCT377E -55 to 125 20 Ld PDIP
CD74HCT377M -55 to 125 20 Ld SOIC
CD74HCT377M96 -55 to 125 20 Ld SOIC

NOTE: Whenordering, use the entire part number. The suffixes
96 and R denote tape and reel.

(oC) PACKAGE

Pinout

CD54HC377, CD54HCT377

(CERDIP)

CD74HC377

(PDIP, SOIC, TSSOP)

CD74HCT377

(PDIP, SOIC)

TOP VIEW

1

E

Q

2

0

D

3

0

D

4

1

Q

5

1

Q

6

2

D

7

2

8

D

3

9

Q

3

GND

10

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© 2004, Texas Instruments Incorporated

1

V

20

CC

Q

19

7

D

18

7

D

17

6

Q

16

6

Q

15

5

D

14

5

D

13

4

12

Q

4

11

CP

CD54HC377, CD74HC377, CD54HCT377, CD74HCT377

Functional Diagram

3

D

0

4

D

1

7

D

2

8

D

3

13

D

4

14

D

5

17

D

6

18

D

7

CP

E

11 1

2

Q

5

Q

6

Q

9

Q

12

Q

15

Q

16

Q

19

Q

GND = 10

= 20

V

CC

0

1

2

3

4

5

6

7

TRUTH TABLE

INPUTS OUPUTS

OPERATING MODE

CP EDnQ

n

Load “1” ↑ lh H
Load “0” ↑ ll L
Hold (Do Nothing) ↑ h X No Change

X H X No Change

H = High Voltage Level Steady State.
h = High Voltage Level One Set-up Time Prior to the Low to High Clock Transition.
L = Low Voltage Level Steady State.
l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition.
X = Don’t Care.
↑ = Low to High Clock Transition.

Logic Diagram

E

CP

D

0

CP

D

1

QD

Q

0

CP

D

2

QD

Q

1

CP

D

3

QD

Q

2

CP

D

4

QD

Q

3

CP

D

5

QD

Q

4

CP

D

6

QD

Q

5

CP

D

7

QD

Q

QD

CP

6

Q

7

2

CD54HC377, CD74HC377, CD54HCT377, CD74HCT377

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

CC

Thermal Resistance (Typical, Note 1) θJA (oC/W)

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 69

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 58

PW (TSSOP) Package. . . . . . . . . . . . . . . . . . . . . . . 83

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

V

IH

V

IL

V

OH

V

OL

I

I

I

CC

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

CC

(V)

o

25

C -40oC TO 85oC -55oC TO 125oC

UNITSV

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - - V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

VCC or

0 6 - - 8 - 80 - 160 µA

GND

3

CD54HC377, CD74HC377, CD54HCT377, CD74HCT377

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

HCT TYPES

High Level Input
Voltage

Low Level Input

V

IH

V

IL

Voltage
High Level Output

Voltage

V

OH

CMOS Loads
High Level Output

Voltage
TTL Loads

Low Level Output

V

OL

Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

I

I

CC

∆I

CC

(Note 2)

Input Pin: 1 Unit Load

NOTE:

2. For dual-supply systems theoretical worst case (V

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

- - 4.5 to

- - 4.5 to

VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V

VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V

VCCand

GND

VCC or

GND

V

CC

-2.1

o

C -40oC TO 85oC -55oC TO 125oC

V

CC

(V)

25

UNITSV

2--2- 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

-4 4.5 3.98 - - 3.84 - 3.7 - V

4 4.5 - - 0.26 - 0.33 - 0.4 V

0 5.5 - - ±0.1 - ±1-±1 µA

0 5.5 - - 8 - 80 - 160 µA

- 4.5 to

- 100 360 - 450 - 490 µA

5.5

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

HCT Input Loading Table

INPUT UNIT LOADS

E 1.5

CP 0.5

All Dn Inputs 0.25

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Table,e.g.,
360µA max at 25oC.

Prerequisite for Switching Specifications

PARAMETER SYMBOL

HC TYPES

Maximum Clock
Frequency

Clock Pulse Width t

f

MAX

W

TEST

CONDITIONS

- 26--5-4-MHz

- 2 80 - - 100 - 120 - ns

V

CC

(V)

4.5 30 - - 25 - 20 - MHz
6 35 - - 29 - 23 - MHz

4.5 16 - - 20 - 24 - ns
614- -17-20-ns

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

4