Texas Instruments CD74HCT368M96, CD74HCT368M, CD74HCT368E, CD74HCT367M96, CD74HCT367M Datasheet
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Data sheet acquired from Harris Semiconductor
/
j
SCHS181
November 1997
CD74HC367, CD74HCT367,
CD74HC368, CD74HCT368
High Speed CMOS Logic Hex Buffer/Line Driver,
Three-State Non-Inverting and Inverting
[ /Title
(CD74
HC367
,
CD74
HCT36
7,
CD74
HC368
,
CD74
HCT36
8)
Subect
(High
Speed
Features
• Buffered Inputs
• High Current Bus Driver Outputs
• Two Independent Three-State Enable Controls
• TypicalPropagation Delay t
C
= 15pF, TA = 25oC
L
PLH,tPHL
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
= 30%, NIH = 30% of V
IL
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), VIH = 2V (Min)
IL
- CMOS Input Compatibility, I
= 8ns at VCC=5V,
≤ 1µA at VOL, V
l
o
C to 125oC
OH
Description
The Harris CD74HC367, CD74HCT367, CD74HC368, and
CD74HCT368 silicon gate CMOS three-state buffers are general purpose high-speed non-inverting and inverting buffers.
They have high drive current outputs which enable high speed
operation even when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuitry, yet
have speeds comparable to low power Schottky TTL circuits.
Both circuits are capable of driving up to 15 lowpower Schottky
inputs.
The CD74HC367 and CD74HCT367 are non-inverting buffers,
whereas the CD74HC368 and CD74HCT368 are inverting buffers. These devices havetwo output enables, one enable (OE1)
controls 4 gates and the other (OE2) controls the remaining 2
gates.
The CD74HCT367 and CD74HCT368 logic families are speed,
function and pin compatible with the standard 74LS logic family .
Ordering Information
CC
PART NUMBER
CD74HC367E -55 to 125 16 Ld PDIP E16.3
CD74HCT367E -55 to 125 16 Ld PDIP E16.3
CD74HCT368E -55 to 125 16 Ld PDIP E16.3
CD74HC367M -55 to 125 16 Ld SOIC M16.15
CD74HCT367M -55 to 125 16 Ld SOIC M16.15
CD74HC368M -55 to 125 16 Ld SOIC M16.15
CD74HCT368M -55 to 125 16 Ld SOIC M16.15
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer or die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
TEMP. RANGE
(oC) PACKAGE PKG. NO.
Pinouts
CD74HC367, CD74HCT367 (PDIP, SOIC)
TOP VIEW
V
1
OE1
2
1A
1Y
3
2A
4
5
2Y
3A
6
7
3Y
GND
8
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1997
16
CC
15
OE2
14
6A
13
6Y
12
5A
5Y
11
10
4A
4Y
9
1
CD74HC368, CD74HCT368 (PDIP, SOIC)
1
OE1
2
1A
3
1Y
4
2A
5
2Y
3A
6
7
3Y
GND
8
TOP VIEW
V
16
CC
15
OE2
14
6A
13
6Y
12
5A
11
5Y
10
4A
9
4Y
File Number 1538.1
CD74HC367, CD74HCT367, CD74HC368, CD74HCT368
Functional Diagrams
CD74HC367, CD74HCT367 CD74HC368, CD74HCT368
OE1
1A
1Y
2A
2Y
3A
3Y
GND
1
2
3
4
5
6
7
8
16
V
CC
15
OE2
14
6A
13
6Y
12
5A
11
5Y
10
4A
9
4Y
OE1
1A
1Y
2A
2Y
3A
3Y
GND
1
2
3
4
5
6
7
8
16
V
CC
15
OE2
14
6A
13
6Y
12
5A
11
5Y
10
4A
9
4Y
TRUTH TABLE
OUTPUTS
INPUTS
(Y)
OE A HC/HCT367 HC/HCT368
LLLH
LHHL
H X (Z) (Z)
NOTE:
H = High Voltage Level
L = Low Voltage Level
X = Don’t Care
Z = High Impedance (OFF) State
2
Logic Diagram
CD74HC367, CD74HCT367, CD74HC368, CD74HCT368
V
CC
16
ONE OF SIX IDENTICAL CIRCUITS
2
1A
3
1Y
8
OE1
OE2
(NOTE)
GND
1
4
15
2A
3A
4A
5A
6A
6
10
12
14
5
2Y
7
3Y
9
4Y
11
5Y
13
6Y
NOTE: Inverter not included in HC/HCT367.
FIGURE 1. LOGIC DIAGRAM FOR THE HC/HCT367 AND HC/HCT368 (OUTPUTS FOR HC/HCT367 ARE COMPLEMENTS OF
THOSE SHOWN, i.e., 1Y, 2Y, ETC.)
3
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