• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), VIH = 2V (Min)
IL
- CMOS Input Compatibility, I
= 30%, NIH = 30% of V
IL
≤ 1µA at VOL, V
l
C to 125oC
OH
Description
The ’HC32 and ’HCT32 contain four 2-input OR gates in one
package. Logic gates utilize silicon gate CMOS technology
to achieve operating speeds similar to LSTTL gates with the
low power consumption of standard CMOS integrated circuits. All devices have the ability to drive 10 LSTTL loads.
The HCT logic family is functionally pin compatible with the
standard LS logic family.
Ordering Information
TEMP. RANGE
CC
PART NUMBER
CD54HC32F3A-55 to 12514 Ld CERDIP
CD54HCT32F3A-55 to 12514 Ld CERDIP
CD74HC32E-55 to 12514 Ld PDIP
CD74HC32M-55 to 12514 Ld SOIC
CD74HC32MT-55 to 12514 Ld SOIC
CD74HC32M96-55 to 12514 Ld SOIC
CD74HCT32E-55 to 12514 Ld PDIP
CD74HCT32M-55 to 12514 Ld SOIC
(oC)PACKAGE
Pinout
CD74HCT32MT-55 to 12514 Ld SOIC
CD74HCT32M96-55 to 12514 Ld SOIC
NOTE: Whenordering, usetheentire part number.The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
CD54HC32, CD54HCT32
(CERDIP)
CD74HC32, CD74HCT32
(PDIP, SOIC)
TOP VIEW
1A
1
2
1B
3
1Y
4
2A
5
2B
6
2Y
7
GND
14
V
CC
4B
13
12
4A
4Y
11
3B
10
3A
9
3Y
8
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
Maximum Junction Temperature (Hermetic P ac kage or Die) . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CC
DC Electrical Specifications
PARAMETERSYMBOL
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
V
IH
V
IL
V
OH
V
OL
I
I
I
CC
TEST
CONDITIONS
25oC-40oC TO 85oC-55oC TO 125oC
VCC (V)
--21.5--1.5-1.5-V
4.53.15--3.15 -3.15-V
64.2--4.2-4.2-V
--2--0.5-0.5-0.5V
4.5--1.35-1.35-1.35V
6--1.8-1.8-1.8V
VIH or
V
-0.0221.9--1.9-1.9-V
IL
-0.024.54.4--4.4 -4.4-V
-0.0265.9--5.9-5.9-V
-44.53.98--3.84-3.7-V
-5.265.48--5.34-5.2-V
VIH or
V
0.022--0.1-0.1-0.1V
IL
0.024.5--0.1-0.1-0.1V
0.026--0.1-0.1-0.1V
44.5--0.26-0.33-0.4V
5.26--0.26-0.33-0.4V
VCC or
-6--±0.1-±1-±1µA
GND
VCC or
06--2-20-40µA
GND
UNITSVI(V)IO(mA)MINTYPMAXMINMAXMINMAX
3
CD54HC32, CD74HC32, CD54HCT32, CD74HCT32
DC Electrical Specifications (Continued)
TEST
CONDITIONS
PARAMETERSYMBOL
HCT TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
V
IH
V
IL
V
OH
V
OL
I
I
I
CC
∆I
CC
(Note 2)
--4.5 to
--4.5 to
VIH or
V
VIH or
V
V
CC
-0.024.54.4--4.4-4.4-V
IL
-0.024.5--0.1-0.1-0.1V
IL
and
GND
VCC or
GND
V
CC
-2.1
25oC-40oC TO 85oC-55oC TO 125oC
VCC (V)
UNITSVI(V)IO(mA)MINTYPMAXMINMAXMINMAX
2-- 2 - 2 - V
5.5
--0.8-0.8-0.8V
5.5
-44.53.98--3.84-3.7-V
44.5--0.26-0.33-0.4V
-5.5-±0.1-±1-±1µA
05.5--2-20-40µA
-4.5 to
-100360-450-490µA
5.5
NOTE:
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUTUNIT LOADS
All1.5
NOTE: Unit Load is ∆ICClimit specified in DC Electrical
Specifications table, e.g., 360µA max at 25oC.
Switching Specifications Input t
PARAMETERSYMBOL
HC TYPES
Propagation Delay, Input to
Output (Figure 1)
PropagationDelay,DataInputto
Output Y
Transition Times (Figure 1)t
t
PLH
t
PLH
TLH
, tf = 6ns
r
, t
PHLCL
, t
PHLCL
, t
THLCL
TEST
CONDITIONS
V
CC
(V)
25oC-40oC TO 85oC -55oC TO 125oC
= 50pF2--90-115-135ns
4.5--18-23-27ns
6--15-20-23ns
= 15pF5-7-----ns
= 50pF2--75-95-110ns
4.5--15-19-22ns
6--13-16-19ns
UNITSMIN TYP MAXMINMAXMINMAX
4
CD54HC32, CD74HC32, CD54HCT, CD74HCT32
Switching Specifications Input t
PARAMETERSYMBOL
Input CapacitanceC
Power Dissipation Capacitance
, tf = 6ns (Continued)
r
TEST
CONDITIONS
I
C
PD
----10-10-10pF
- 5-22-----pF
V
CC
(V)
(Notes 3, 4)
HCT TYPES
Propagation Delay, Input to
t
RHL
, t
PHLCL
= 50pF4.5--24-30-36ns
Output (Figure 2)
PropagationDelay,DataInputto
t
PLH
, t
PHLCL
= 15pF5-9-----ns
Output Y
Transition Times (Figure 2)t
Input CapacitanceC
Power Dissipation Capacitance
TLH
, t
I
C
PD
THLCL
= 50pF4.5--15-19-22ns
----10-10-10pF
- 5-22-----pF
(Notes 3, 4)
NOTES:
3. CPD is used to determine the dynamic power consumption, per gate.
4. PD = V
2
fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
CC
Test Circuits and Waveforms
25oC-40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAXMINMAXMINMAX
tr = 6nstf = 6ns
V
t
CC
GND
TLH
INPUT
t
INVERTING
OUTPUT
THL
t
PHL
90%
50%
10%
t
90%
50%
10%
PLH
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
= 6ns
t
PLH
t
f
1.3V
10%
90%
t
3V
GND
TLH
tr = 6ns
INPUT
t
INVERTING
OUTPUT
THL
t
PHL
2.7V
1.3V
0.3V
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5
PACKAGE OPTION ADDENDUM
www.ti.com
PACKAGING INFORMATION
Orderable DeviceStatus
5962-8685201CAACTIVECDIPJ141TBDA42 SNPBN / A for Pkg Type
CD54HC32F3AACTIVECDIPJ141TBDA42 SNPBN / A for Pkg Type
CD54HCT32FACTIVECDIPJ141TBDA42 SNPBN / A for Pkg Type
CD54HCT32F3AACTIVECDIPJ141TBDA42 SNPBN / A for Pkg Type
CD74HC32EACTIVEPDIPN1425Pb-Free
CD74HC32EE4ACTIVEPDIPN1425Pb-Free
CD74HC32MACTIVESOICD1450Green (RoHS &
CD74HC32M96ACTIVESOICD142500 Green (RoHS &
CD74HC32M96E4ACTIVESOICD142500 Green (RoHS &
CD74HC32M96G4ACTIVESOICD142500 Green (RoHS &
CD74HC32ME4ACTIVESOICD1450Green (RoHS &
CD74HC32MG4ACTIVESOICD1450Green (RoHS &
CD74HC32MTACTIVESOICD14250 Green (RoHS &
CD74HC32MTE4ACTIVESOICD14250 Green(RoHS &
CD74HC32MTG4ACTIVESOICD14250 Green (RoHS &
CD74HCT32EACTIVEPDIPN1425Pb-Free
CD74HCT32EE4ACTIVEPDIPN1425Pb-Free
CD74HCT32MACTIVESOICD1450Green (RoHS &
CD74HCT32M96ACTIVESOICD142500 Green (RoHS &
CD74HCT32M96E4ACTIVESOICD142500 Green (RoHS &
CD74HCT32M96G4ACTIVESOICD142500 Green (RoHS &
CD74HCT32ME4ACTIVESOICD1450Green (RoHS &
CD74HCT32MG4ACTIVESOICD1450Green (RoHS &
CD74HCT32MTACTIVESOICD14250 Green (RoHS &
CD74HCT32MTE4ACTIVESOICD14250 Green(RoHS &
CD74HCT32MTG4ACTIVESOICD14250 Green (RoHS &
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAUN / A for Pkg Type
CU NIPDAUN / A for Pkg Type
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAUN / A for Pkg Type
CU NIPDAUN / A for Pkg Type
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
CU NIPDAULevel-1-260C-UNLIM
9-Oct-2007
(3)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
(1)
The marketing status values are defined as follows:
9-Oct-2007
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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