Texas Instruments CD74HCT30M96, CD74HCT30M, CD74HCT30E, CD74HC30E, CD74HC30PWR Datasheet
...
Data sheet acquired from Harris Semiconductor
/
SCHS121
August 1997
CD54HC30, CD74HC30,
CD74HCT30
High Speed CMOS Logic
8-Input NAND Gate
[ /Title
(CD54H
C30,
CD74H
C30,
CD74H
CT30)
Subject
(High
Speed
CMOS
Logic 8-
Features
• Buffered Inputs
• Typical Propagation Delay: 10ns at V
C
= 15pF, TA = 25oC
L
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), VIH = 2V (Min)
IL
- CMOS Input Compatibility, I
= 30%, NIH = 30% of V
IL
≤ 1µA at VOL, V
l
CC
= 5V,
o
C to 125oC
OH
Description
The Harris CD74HC30, CD74HCT30, each contain an 8-input
NAND gate in one package. They provide the system
designer with the direct implementation of the positive logic
8-input NAND function. Logic gates utilize silicon gate
CMOS technology to achieve operating speeds similar to
LSTTL gates with the low power consumption of standard
CMOS integrated circuits. All devices have the ability to drive
10 LSTTL loads. The 74HCT logic family is functionally pin
compatible with the standard 74LS logic family.
Ordering Information
TEMP.RANGE
CC
PART NUMBER
CD74HC30E -55 to 125 14 Ld PDIP E14.3
CD74HCT30E -55 to 125 14 Ld PDIP E14.3
CD74HC30M -55 to 125 14 Ld SOIC M14.15
CD74HCT30M -55 to 125 14 Ld SOIC M14.15
CD54HCT30H -55 to 125 Die
NOTES:
1. When ordering,use the entire partnumber. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Die for this part number is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.
(oC) PACKAGE
PKG.
NO.
Pinout
CD54HC30, CD74HC30, CD74HCT30
(PDIP, CERDIP, SOIC)
TOP VIEW
A
1
2
B
C
3
D
4
E
5
F
6
GND
7
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1997
1
V
14
CC
NC
13
H
12
G
11
NC
10
NC
9
Y
8
File Number 1652.1
Functional Diagram
LXXXXXXX H
XLXXXXXX H
XXLXXXXX H
XXXLXXXX H
CD54HC30, CD74HC30, CD74HCT30
1
A
2
B
3
C
4
D
5
E
6
F
11
G
12
H
TRUTH TABLE
INPUTS
8
Y =
ABCDEFGH
Y
OUTPUTABCDEFGH
Logic Symbol
XXXXLXXX H
XXXXXLXX H
XXXXXXLX H
XXXXXXXL H
HHHHHHHH L
NOTE: H = HIGH Voltage Level, L = LOW Voltage Level, X = Irrelevant
1
A
2
B
3
C
4
D
5
E
6
F
11
G
8
Y
12
H
2
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