TEXAS INSTRUMENTS CD54HC27 Technical data

Data sheet acquired from Harris Semiconductor

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SCHS132C

August 1997 - Revised September 2003

CD54HC27, CD74HC27,

CD54HCT27, CD74HCT27

High-Speed CMOS Logic

Triple 3-Input NOR Gate

/Title
CD74

C27,
D74
CT27

Sub­ect
High

peed

MOS

ogic

Features

• Buffered Inputs

• Typical Propagation Delay: 7ns at V
C

= 15pF, TA = 25oC

L

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

CC

= 5V,

o

C to 125oC

OH

Description

The ’HC27and ’HCT27 logic gates utilize silicon gate CMOS
technology to achieve operating speeds similar to LSTTL
gates with the low power consumption of standard CMOS
integrated circuits. All devices have the ability to drive 10
LSTTL loads. The HCT logic family is functionally pin
compatible with the standard LS logic family.

Ordering Information

TEMP. RANGE

CC

PART NUMBER

CD54HC27F3A -55 to 125 14 Ld CERDIP
CD54HCT27F3A -55 to 125 14 Ld CERDIP
CD74HC27E -55 to 125 14 Ld PDIP
CD74HC27M -55 to 125 14 Ld SOIC
CD74HC27MT -55 to 125 14 Ld SOIC
CD74HC27M96 -55 to 125 14 Ld SOIC
CD74HCT27E -55 to 125 14 Ld PDIP
CD74HCT27M -55 to 125 14 Ld SOIC
CD74HCT27MT -55 to 125 14 Ld SOIC

(oC) PACKAGE

Pinout

CD74HCT27M96 -55 to 125 14 Ld SOIC

NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel.
of 250.

CD54HC27, CD54HCT27

(CERDIP)

CD74HC27, CD74HCT27

(PDIP, SOIC)

TOP VIEW

1A

1
2

1B

3

2A

4

2B

5

2C

6

2Y

7

GND

The suffix T denotes a small-quantity reel

14

V

CC

1C

13
12

1Y
3C

11

3B

10

3A

9

3Y

8

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© 2003, Texas Instruments Incorporated

1

Functional Diagram

CD54HC27, CD74HC27, CD54HCT27, CD74HCT27

1A

1B

2A

2B

2C

2Y

GND

1

2

3

4

5

6

7

14

V

CC

13

1C

12

1Y

11

3C

10

3B

9

3A

8

3Y

TRUTH TABLE

INPUTS OUTPUT

nA nB nC nY

LLLH
LLHL
LHLL

Logic Symbol

HLLL
HHLL
LHHL
HLHL
HHHL

H = High Voltage Level, L = Low Voltage Level

nA

nB

nC

nY

2

CD54HC27, CD74HC27, CD54HCT27, CD74HCT27

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

CC

Thermal Resistance (Typical, Note 1) θJA (oC/W)

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 80

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 86

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

V

IH

V

IL

V

OH

V

OL

I

I

TEST

CONDITIONS

25oC -40oC TO 85oC -55oC TO 125oC

VCC (V)

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

---------V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIH or

V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

---------V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

3

CD54HC27, CD74HC27, CD54HCT27, CD74HCT27

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Quiescent Device
Current

I

CC

VCC or

GND

VCC (V)

0 6 - - 2 - 20 - 40 µA

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

- - 4.5 to

5.5

V

IL

- - 4.5 to

5.5

V

OH

VIH or

V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

CMOS Loads
High Level Output

-4 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads

Low Level Output
Voltage

V

OL

VIH or

V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

CMOS Loads
Low Level Output

4 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads

Input Leakage
Current

I

I

V

CC

0 5.5 - ±0.1 - ±1-±1 µA

and

GND

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

CC

∆I

CC

(Note 2)

VCC or

GND

V

CC

-2.1

0 5.5 - - 2 - 20 - 40 µA

- 4.5 to

5.5

Input Pin: 1 Unit Load

NOTE:

2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

25oC -40oC TO 85oC -55oC TO 125oC

2-- 2 - 2 - V

- - 0.8 - 0.8 - 0.8 V

- 100 360 - 450 - 490 µA

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

All 1.5

NOTE: Unit Load is ∆ICClimit specified in DC Electrical
Specifications table, e.g. 360µA max at 25oC.

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay, Input to
Output (Figure 1)

PropagationDelay,DataInputto
Output Y

t

PLH

t

PLH

, tf = 6ns

r

, t

PHLCL

, t

PHLCL

TEST

CONDITIONS

= 50pF 2 - - 95 - 120 - 145 ns

= 15pF 5 - 7 - ----ns

V

CC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

4.5 - - 19 - 24 - 29 ns
6 - - 16 - 20 - 25 ns

4