TEXAS INSTRUMENTS CD54HC259F3A, CD54HCT259F3A, CD74HC259E, CD74HC259M, CD74HC259MT Technical data

Data sheet acquired from Harris Semiconductor
SCHS173C

November 1997 - Revised October 2003

CD54HC259, CD74HC259,

CD54HCT259, CD74HCT259

High-Speed CMOS Logic

8-Bit Addressable Latch

[ /Title
(CD74
HC259
,

D74

C
HCT25

9)
/Sub­ject
(High
Speed
CMOS
Logic
8-Bit
Addres
sable
Latch)

Features

• Buffered Inputs and Outputs

• Four Operating Modes

• Typical Propagation Delay of 15ns at V
C

= 15pF, TA = 25oC

L

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

CC

= 5V,

o

C to 125oC

OH

Description

The ’HC259 and ’HCT259 Addressable Latch features the
low-power consumption associated with CMOS circuitry and
has speeds comparable to low-power Schottky.

This latches three active modes and one reset mode. When
both the Latch Enable (
low (8-line Demultiplexer mode) the output of the addressed
latch follo ws the Data input and all other outputs are forced
low . When both
outputs are isolated from the Data input, i.e., all latches hold
the last data presented before the
high. A condition of
mode) allows the addressed latch’s output to follow the data
input; all other latches are unaffected. The Reset mode (all
outputs low) results when

LE) and Master Reset (MR) inputs are

MR and LE are high (Memory Mode), all

LE transition from low to

LE low and MR high (Addressable Latch

LE is high and MR is low.

Ordering Information

CC

PART NUMBER

CD54HC259F3A -55 to 125 16 Ld CERDIP
CD54HCT259F3A -55 to 125 16 Ld CERDIP
CD74HC259E -55 to 125 16 Ld PDIP
CD74HC259M -55 to 125 16 Ld SOIC

TEMP. RANGE

(oC) PACKAGE

CD74HC259MT -55 to 125 16 Ld SOIC
CD74HC259M96 -55 to 125 16 Ld SOIC
CD74HCT259E -55 to 125 16 Ld PDIP
CD74HCT259M -55 to 125 16 Ld SOIC
CD74HCT259MT -55 to 125 16 Ld SOIC
CD74HCT259M96 -55 to 125 16 Ld SOIC

NOTE: Whenordering, use the entire partnumber.The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© 2003, Texas Instruments Incorporated

1

CD54HC259, CD74HC259, CD54HCT259, CD74HCT259

Pinout

Functional Diagram

CD54HC259, CD54HCT259

(CERDIP)

CD74HC259, CD74HCT259

(PDIP, SOIC)

TOP VIEW

1

A0

2

A1

3

A2

4

Q0

5

Q1

6

Q2

7

Q3

8

GND

1

A

0

2

A

A

LE

MR

1

2

D

1-OF-8

DECODER

3

14

15
13

8

LATCHES

16
15
14
13
12
11
10

9

V

CC

MR
LE
D
Q7
Q6
Q5
Q4

4

5

6

7

9

10

11

12

GND = 8
V

CC

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

= 16

TRUTH TABLE

INPUTS OUTPUT OF

ADDRESS

LATCH

EACH OTHER

OUTPUT FUNCTIONMR LE

HL D QioAddressable

Latch

HH Q

io

Q

io

Memory

L L D L 8-Line

Demultiplexer

L H L L Reset

H = High Voltage Level
L = Low Voltage Level
D = The level at the data input
Qio= The level of Qi(i = 0, 1...7, as appropriate) before the indicat­ed steady-state input conditions were established.

LATCH SELECTION TABLE

SELECT INPUTS

ADDRESSEDA2 A1 A0

LLL 0
LLH 1
LHL 2

LHH 3
HLL 4
HLH 5
HHL 6
HHH 7

2

LATCH

CD54HC259, CD74HC259, CD54HCT259, CD74HCT259

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

CC

Thermal Resistance (Typical, Note 1) θJA (oC/W)

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

V

IH

V

IL

V

OH

V

OL

I

I

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

CC

(V)

o

C -40oC TO 85oC -55oC TO 125oC

25

UNITSV

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - - V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

3

CD54HC259, CD74HC259, CD54HCT259, CD74HCT259

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Quiescent Device

I

CC

Current

HCT TYPES

High Level Input

V

IH

Voltage
Low Level Input

Voltage
High Level Output

V

IL

V

OH

Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output

V

OL

Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device

I

I

I

CC

Current
Additional Quiescent

Device Current Per

∆I

CC

(Note 2)

Input Pin: 1 Unit Load

NOTE:

2. For dual-supply systems theoretical worst case (V

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

VCC or

GND

- - 4.5 to

- - 4.5 to

VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V

VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V

VCCand

GND

VCC or

GND
V

CC

-2.1

o

C -40oC TO 85oC -55oC TO 125oC

V

CC

(V)

25

UNITSV

0 6 - - 8 - 80 - 160 µA

2--2- 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

-4 4.5 3.98 - - 3.84 - 3.7 - V

4 4.5 - - 0.26 - 0.33 - 0.4 V

0 5.5 - ±0.1 - ±1-±1 µA

0 5.5 - - 8 - 80 - 160 µA

- 4.5 to

- 100 360 - 450 - 490 µA

5.5

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

HCT Input Loading Table

INPUT UNIT LOADS

A0 - A2, LE 1.5

D 1.2

MR 0.75

NOTE: Unit Load is ∆ICClimit specified in DC ElectricalTable, e.g.,
360µA max at 25oC.

Prerequisite for Switching Specifications

25oC -40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL VCC(V)

HC TYPES

Pulse Width t

LE 2 70 - - 90 - - 105 - - ns

WL

4.5 14 - - 18 - - 21 - - ns
612- -15- -18--ns

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

4

CD54HC259, CD74HC259, CD54HCT259, CD74HCT259

Prerequisite for Switching Specifications (Continued)

25oC -40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL VCC(V)

MR t

Setup Time t

D to LE
A to LE

Hold Time t

D to LE
A to LE

HCT TYPES

Pulse Width

LE
MR

Setup Time

D to LE
A to LE

t

t

WL

SU

H

WL

SU

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

2 70 - - 90 - - 105 - - ns

4.5 14 - - 18 - - 21 - - ns
612- -15- -18--ns

2 80 - - 100 - - 120 - - ns

4.5 16 - - 20 - - 24 - - ns
614- -17- -20--ns

20--0--0--ns

4.5 0 - - 0 - - 0 - - ns
60--0--0--ns

4.5 18 - - 23 - - 27 - - ns

4.5 17 - - 21 - - 26 - - ns

Hold Time

D to LE
A to LE

Switching Specifications C

PARAMETER SYMBOL

HC TYPES

Propagation Delay t

D to Q 2 - - 185 - 230 - 280 ns

LE to Q t

t

H

4.5 0 - - 0 - - 0 - - ns

= 50pF, Input tr, tf= 6ns

L

CONDITIONS VCC(V)

PHL

PHL

CL = 50pF

CL = 15pF 5 - 15 - - - - - ns
CL = 50pF 6 - - 31 - 39 - 48 ns
CL = 50pF 2 - - 170 - 215 - 255 ns

CL = 15pF 5 - 14 - - - - - ns
CL = 50pF 6 - - 29 - 37 - 43 ns

TEST

-40oC TO

25oC

4.5 - - 37 - 46 - 56 ns

4.5 - - 34 - 43 - 51 ns

85oC

-55oC TO
125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

5